Patents by Inventor Masataka Itoh
Masataka Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11122693Abstract: Described are processes for developing laminated circuit boards, as well as the resulting circuit boards themselves. Accordingly, at least two circuit boards at least partially overlap each other, and at least one through-hole is formed in an overlapping region thereof. The through-hole is filled with an electrically-conductive material, forming a through-via that enables the circuit boards to be electrically connected. When a circuit on each circuit board is laid out so that a part thereof reaches a region in which the through-via is to be formed, then that part of the circuit can be electrically connected to the through-via. Thus, portions of the circuits on the circuit boards can be electrically connected to each other via common through-vias to realize an integrated device in which the circuits on the laminated circuit boards function.Type: GrantFiled: August 14, 2017Date of Patent: September 14, 2021Assignee: Pi-Crystal IncorporationInventors: Junichi Takeya, Seiichiro Yamaguchi, Masataka Itoh
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Patent number: 10451943Abstract: Active matrix array devices are constituted by devices that have a function such as those of a display/light emitting device, a sensor, a memory or an actuator, and are arranged in a matrix array shape, and the expansion of usage in various fields and applications is expected. However, there is little similarity and compatibility in the forming process and materials between a device such as a display/light emitting device, a sensor, a memory, or an actuator, and a circuit portion that controls such a device in the matrix element, and therefore the device and the circuit portion are mutually restricting factors. This results in an increase in the manufacturing cost and limitation of the function. A conventional active matrix array device is manufactured by performing various process steps on the same substrate. Control circuit portions each including a transistor are formed in some of the process steps.Type: GrantFiled: April 20, 2016Date of Patent: October 22, 2019Assignee: PI-CRYSTAL INC.Inventors: Seiichiro Yamaguchi, Junichi Takeya, Masataka Itoh, Norikazu Shomoto, Mina Uematsu
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Publication number: 20190313535Abstract: Research on practical realization of various types of printable devices has progressed, and the realization of devices in which these printable devices are integrated on a flexible board is expected. However, there is the problem that, if a plurality of printable devices are simply integrated on the same board, the area of the integrated device increases, and the yield ratio greatly decreases. An integration technique that solves the problem of an increase in the area and a decrease in the yield ratio is in demand. Electronic devices to be integrated are formed on individual boards, the boards are laid to overlap each other in a predetermined relationship, and then through-vias are formed at predetermined positions. With this, the electronic devices are electrically connected to each other, and function as an integrated device.Type: ApplicationFiled: June 24, 2019Publication date: October 10, 2019Inventors: Junichi TAKEYA, Seiichiro YAMAGUCHI, Masataka ITOH
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Publication number: 20180107083Abstract: Active matrix array devices are constituted by devices that have a function such as those of a display/light emitting device, a sensor, a memory or an actuator, and are arranged in a matrix array shape, and the expansion of usage in various fields and applications is expected. However, there is little similarity and compatibility in the forming process and materials between a device such as a display/light emitting device, a sensor, a memory, or an actuator, and a circuit portion that controls such a device in the matrix element, and therefore the device and the circuit portion are mutually restricting factors. This results in an increase in the manufacturing cost and limitation of the function. A conventional active matrix array device is manufactured by performing various process steps on the same substrate. Control circuit portions each including a transistor are formed in some of the process steps.Type: ApplicationFiled: April 20, 2016Publication date: April 19, 2018Inventors: Seiichiro YAMAGUCHI, Junichi TAKEYA, Masataka ITOH, Norikazu SHOMOTO, Mina UEMATSU
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Publication number: 20170374746Abstract: Research on practical realization of various types of printable devices has progressed, and the realization of devices in which these printable devices are integrated on a flexible board is expected. However, there is the problem that, if a plurality of printable devices are simply integrated on the same board, the area of the integrated device increases, and the yield ratio greatly decreases. An integration technique that solves the problem of an increase in the area and a decrease in the yield ratio is in demand. Electronic devices to be integrated are formed on individual boards, the boards are laid to overlap each other in a predetermined relationship, and then through-vias are formed at predetermined positions. With this, the electronic devices are electrically connected to each other, and function as an integrated device.Type: ApplicationFiled: August 14, 2017Publication date: December 28, 2017Inventors: Junichi TAKEYA, Seiichiro YAMAGUCHI, Masataka ITOH
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Patent number: 7764273Abstract: A touch panel includes a TFT array having a plurality of thin film transistors; a plurality of signal lines disposed within the TFT array, each of the signal lines being electrically connected to a respective one of the transistors; a transparent conductive pattern layer disposed above the plurality of signal lines and electrically connected to each of the transistors; a flexible conductive layer; and a spacing pattern layer supporting flexible conductive layer to space the flexible conductive layer apart from the transparent conductive pattern layer. When pressure is applied onto the flexible conductive layer, the flexible conductive layer contacts the transparent conductive pattern layer to transmit an electrical signal via the signal lines into the TFTs to indicate the point of contact.Type: GrantFiled: December 27, 2004Date of Patent: July 27, 2010Assignee: Au Optronics CorporationInventors: Chien-Sen Weng, Masataka Itoh
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Publication number: 20060001651Abstract: A touch panel includes a TFT array having a plurality of thin film transistors; a plurality of signal lines disposed within the TFT array, each of the signal lines being electrically connected to a respective one of the transistors; a transparent conductive pattern layer disposed above the plurality of signal lines and electrically connected to each of the transistors; a flexible conductive layer; and a spacing pattern layer supporting flexible conductive layer to space the flexible conductive layer apart from the transparent conductive pattern layer. When pressure is applied onto the flexible conductive layer, the flexible conductive layer contacts the transparent conductive pattern layer to transmit an electrical signal via the signal lines into the TFTs to indicate the point of contact.Type: ApplicationFiled: December 27, 2004Publication date: January 5, 2006Inventors: Chien-Sen Weng, Masataka Itoh
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Patent number: 6784495Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.Type: GrantFiled: November 8, 2002Date of Patent: August 31, 2004Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Jun Koyama, Hidehito Kitakado, Masataka Itoh, Hiroyuki Ogawa
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Patent number: 6558993Abstract: There is provided a semiconductor device using a TFT structure of high reliability. A gate electrode of a TFT includes a first conductive layer, a second conductive layer, and a third conductive layer. An LDD region has a part which overlaps the gate electrode via a gate insulating film and a part which does not overlap the gate electrode. As a result, this can prevent the deterioration when the TFT is on and can reduce a leakage current when the TFT is off.Type: GrantFiled: May 17, 2001Date of Patent: May 6, 2003Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Hisashi Ohtani, Shunpei Yamazaki, Masataka Itoh
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Publication number: 20030075761Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.Type: ApplicationFiled: November 8, 2002Publication date: April 24, 2003Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Jun Koyama, Hidehito Kitakado, Masataka Itoh, Hiroyuki Ogawa
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Publication number: 20030053765Abstract: The present invention provides a photo-electric combined substrate comprising an electric interconnection part having an electric interconnection layer and an electric insulating layer as well as an optical waveguide part consisting of a core and a clad, where the electric insulating layer in the electric interconnection part and the optical waveguide part are made of the same material; a ceramic substrate comprising an optical device and an electric device where a ceramic substrate has a concave where the concave is filled with a resin, and where at least an optical device is mounted on the ceramic substrate while an electric device on the resin in the substrate concave; and an optical waveguide comprising a core and a clad having a refractive index lower than that of the core, where the core is made of a fluorene-unit-containing epoxy acrylate resin.Type: ApplicationFiled: September 26, 2002Publication date: March 20, 2003Applicant: NEC CORPORATIONInventors: Mikio Oda, Sakae Kitajo, Yuzo Shimada, Masataka Itoh, Yoshinobu Kaneyama, Masahiko Fujiwara
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Patent number: 6492681Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.Type: GrantFiled: March 6, 2001Date of Patent: December 10, 2002Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Jun Koyama, Hidehito Kitakado, Masataka Itoh, Hiroyuki Ogawa
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Patent number: 6477284Abstract: The present invention provides a photo-electric combined substrate comprising an electric interconnection part having an electric interconnection layer and an electric insulating layer as well as an optical waveguide part consisting of a core and a clad, where the electric insulating layer in the electric interconnection part and the optical waveguide part are made of the same material; a ceramic substrate comprising an optical device and an electric device where a ceramic substrate has a concave where the concave is filled with a resin, and where at least an optical device is mounted on the ceramic substrate while an electric device on the resin in the substrate concave; and an optical waveguide comprising a core and a clad having a refractive index lower than that of the core, where the core is made of a fluorene-unit-containing epoxy acrylate resin.Type: GrantFiled: June 13, 2000Date of Patent: November 5, 2002Assignee: NEC CorporationInventors: Mikio Oda, Sakae Kitajo, Yuzo Shimada, Masataka Itoh, Yoshinobu Kaneyama, Masahiko Fujiwara
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Patent number: 6393171Abstract: The integrity of a solder jointing pad, which is used to mount an optical module, is enhanced by avoiding exposure to high temperatures used in the formation of an accompanying optical wave guide. The enhanced integrity of the solder jointing pad permits a mounting solder bump to be evenly distributed on the pad, which improves mounting position characteristics. The solder jointing pads are elongated in shape and arranged in parallel and perpendicular orientation with respect to an optical transmission path in the optical module. The enhanced integrity of the solder jointing pads permits a precise amount of solder to be introduced to the pads when mounting the optical module. The optical module can then be precisely positioned simply by varying the amount of solder introduced to the solder jointing pads. The optical device can be positioned with high accuracy by taking advantage of the self-alignment action which occurs between the molten solder bumps and the solder jointing pads.Type: GrantFiled: June 20, 2001Date of Patent: May 21, 2002Assignee: NEC CorporationInventors: Junichi Sasaki, Masataka Itoh, Naoki Kitamura
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Publication number: 20020033513Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.Type: ApplicationFiled: March 6, 2001Publication date: March 21, 2002Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Jun Koyama, Hidehito Kitakado, Masataka Itoh, Hiroyuki Ogawa
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Publication number: 20010033718Abstract: The integrity of a solder jointing pad, which is used to mount an optical module, is enhanced by avoiding exposure to high temperatures used in the formation of an accompanying optical wave guide. The enhanced integrity of the solder jointing pad permits a mounting solder bump to be evenly distributed on the pad, which improves mounting position characteristics. The solder jointing pads are elongated in shape and arranged in parallel and perpendicular orientation with respect to an optical transmission path in the optical module. The enhanced integrity of the solder jointing pads permits a precise amount of solder to be introduced to the pads when mounting the optical module. The optical module can then be precisely positioned simply by varying the amount of solder introduced to the solder jointing pads. The optical device can be positioned with high accuracy by taking advantage of the self-alignment action which occurs between the molten solder bumps and the solder jointing pads.Type: ApplicationFiled: June 20, 2001Publication date: October 25, 2001Applicant: NEC CorporationInventors: Junichi Sasaki, Masataka Itoh, Naoki Kitamura
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Patent number: 6298861Abstract: A wig stopper including a bent, counter-bendable, component that is obtained by processing a single elastic thin sheet to bend and impart a counter-bendable characteristic thereto. The wig stopper further includes a number of hair-fastening components, each having a base end part provided on the longitudinal side of the upper end of the bent, counter-bendable, component. Also, a tip end part is extended to the longitudinal side of the lower end of the bent, counter-bendable, component such that the hair-fastening components are arranged in a comb-tooth fashion.Type: GrantFiled: October 19, 1999Date of Patent: October 9, 2001Assignee: Aderans Co., Ltd.Inventors: Masanori Kageyama, Masataka Itoh
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Publication number: 20010025960Abstract: There is provided a semiconductor device using a TFT structure of high reliability.Type: ApplicationFiled: May 17, 2001Publication date: October 4, 2001Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Shunpei Yamazaki, Masataka Itoh
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Patent number: 6259138Abstract: A semiconductor device using a TFT including a multilayered gate electrode and an LDD region partially overlapping with the multilayered gate electrode via a gate insulating film is provided.Type: GrantFiled: December 16, 1999Date of Patent: July 10, 2001Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Hisashi Ohtani, Shunpei Yamazaki, Masataka Itoh
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Patent number: 6238100Abstract: A semiconductor optical amplifier is mounted on a substrate which is provided for a package. Fiber blocks in which plural parallel internal optical fibers are supported are fitted to the package. The optical fibers are optically coupled with the semiconductor optical amplifier via optical waveguides formed on the substrate. V grooves for supporting the optical fibers which protrude out from the fiber block are formed on the substrate. Positionings of the optical fibers are performed by fitting the fiber blocks to the package so that end faces of the optical fibers butt against end walls of the V grooves.Type: GrantFiled: October 20, 1999Date of Patent: May 29, 2001Assignee: NEC CorporationInventors: Junichi Sasaki, Tomoaki Kato, Masataka Itoh