Patents by Inventor Masataka Itoh

Masataka Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190313535
    Abstract: Research on practical realization of various types of printable devices has progressed, and the realization of devices in which these printable devices are integrated on a flexible board is expected. However, there is the problem that, if a plurality of printable devices are simply integrated on the same board, the area of the integrated device increases, and the yield ratio greatly decreases. An integration technique that solves the problem of an increase in the area and a decrease in the yield ratio is in demand. Electronic devices to be integrated are formed on individual boards, the boards are laid to overlap each other in a predetermined relationship, and then through-vias are formed at predetermined positions. With this, the electronic devices are electrically connected to each other, and function as an integrated device.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: Junichi TAKEYA, Seiichiro YAMAGUCHI, Masataka ITOH
  • Patent number: 10333280
    Abstract: A configuration of a DFB laser-based wavelength tunable laser is well known, but long resonators have difficulty in forming uniform resonators due to production variations, thereby inducing limitation in narrowing the spectral linewidth in the DFB laser-based wavelength tunable laser as well. In the semiconductor laser device of the present invention, a semiconductor laser that oscillates in a single mode and a low-loss lightwave circuit using SiO2 glass are arranged on the common substrate. The lightwave circuit is configured such that part of output light from the semiconductor laser propagates through a certain length of an optical path, and then is reflected by a reflector and is fed back to the semiconductor laser. Output light from the semiconductor laser and an input waveguide of the lightwave circuit can also be configured to be optically connected directly to each other. The present invention can provide a compact laser device with a narrowed spectral linewidth and stable wavelength controllability.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 25, 2019
    Assignees: Nippon Telegraph and Telephone Corporation, Tohoku University
    Inventors: Hiroyuki Ishii, Naoki Fujiwara, Kei Watanabe, Mikitaka Itoh, Keisuke Kasai, Masataka Nakazawa
  • Publication number: 20180107083
    Abstract: Active matrix array devices are constituted by devices that have a function such as those of a display/light emitting device, a sensor, a memory or an actuator, and are arranged in a matrix array shape, and the expansion of usage in various fields and applications is expected. However, there is little similarity and compatibility in the forming process and materials between a device such as a display/light emitting device, a sensor, a memory, or an actuator, and a circuit portion that controls such a device in the matrix element, and therefore the device and the circuit portion are mutually restricting factors. This results in an increase in the manufacturing cost and limitation of the function. A conventional active matrix array device is manufactured by performing various process steps on the same substrate. Control circuit portions each including a transistor are formed in some of the process steps.
    Type: Application
    Filed: April 20, 2016
    Publication date: April 19, 2018
    Inventors: Seiichiro YAMAGUCHI, Junichi TAKEYA, Masataka ITOH, Norikazu SHOMOTO, Mina UEMATSU
  • Publication number: 20170374746
    Abstract: Research on practical realization of various types of printable devices has progressed, and the realization of devices in which these printable devices are integrated on a flexible board is expected. However, there is the problem that, if a plurality of printable devices are simply integrated on the same board, the area of the integrated device increases, and the yield ratio greatly decreases. An integration technique that solves the problem of an increase in the area and a decrease in the yield ratio is in demand. Electronic devices to be integrated are formed on individual boards, the boards are laid to overlap each other in a predetermined relationship, and then through-vias are formed at predetermined positions. With this, the electronic devices are electrically connected to each other, and function as an integrated device.
    Type: Application
    Filed: August 14, 2017
    Publication date: December 28, 2017
    Inventors: Junichi TAKEYA, Seiichiro YAMAGUCHI, Masataka ITOH
  • Patent number: 7764273
    Abstract: A touch panel includes a TFT array having a plurality of thin film transistors; a plurality of signal lines disposed within the TFT array, each of the signal lines being electrically connected to a respective one of the transistors; a transparent conductive pattern layer disposed above the plurality of signal lines and electrically connected to each of the transistors; a flexible conductive layer; and a spacing pattern layer supporting flexible conductive layer to space the flexible conductive layer apart from the transparent conductive pattern layer. When pressure is applied onto the flexible conductive layer, the flexible conductive layer contacts the transparent conductive pattern layer to transmit an electrical signal via the signal lines into the TFTs to indicate the point of contact.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: July 27, 2010
    Assignee: Au Optronics Corporation
    Inventors: Chien-Sen Weng, Masataka Itoh
  • Publication number: 20060001651
    Abstract: A touch panel includes a TFT array having a plurality of thin film transistors; a plurality of signal lines disposed within the TFT array, each of the signal lines being electrically connected to a respective one of the transistors; a transparent conductive pattern layer disposed above the plurality of signal lines and electrically connected to each of the transistors; a flexible conductive layer; and a spacing pattern layer supporting flexible conductive layer to space the flexible conductive layer apart from the transparent conductive pattern layer. When pressure is applied onto the flexible conductive layer, the flexible conductive layer contacts the transparent conductive pattern layer to transmit an electrical signal via the signal lines into the TFTs to indicate the point of contact.
    Type: Application
    Filed: December 27, 2004
    Publication date: January 5, 2006
    Inventors: Chien-Sen Weng, Masataka Itoh
  • Patent number: 6784495
    Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: August 31, 2004
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Jun Koyama, Hidehito Kitakado, Masataka Itoh, Hiroyuki Ogawa
  • Patent number: 6558993
    Abstract: There is provided a semiconductor device using a TFT structure of high reliability. A gate electrode of a TFT includes a first conductive layer, a second conductive layer, and a third conductive layer. An LDD region has a part which overlaps the gate electrode via a gate insulating film and a part which does not overlap the gate electrode. As a result, this can prevent the deterioration when the TFT is on and can reduce a leakage current when the TFT is off.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: May 6, 2003
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hisashi Ohtani, Shunpei Yamazaki, Masataka Itoh
  • Publication number: 20030075761
    Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.
    Type: Application
    Filed: November 8, 2002
    Publication date: April 24, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hidehito Kitakado, Masataka Itoh, Hiroyuki Ogawa
  • Publication number: 20030053765
    Abstract: The present invention provides a photo-electric combined substrate comprising an electric interconnection part having an electric interconnection layer and an electric insulating layer as well as an optical waveguide part consisting of a core and a clad, where the electric insulating layer in the electric interconnection part and the optical waveguide part are made of the same material; a ceramic substrate comprising an optical device and an electric device where a ceramic substrate has a concave where the concave is filled with a resin, and where at least an optical device is mounted on the ceramic substrate while an electric device on the resin in the substrate concave; and an optical waveguide comprising a core and a clad having a refractive index lower than that of the core, where the core is made of a fluorene-unit-containing epoxy acrylate resin.
    Type: Application
    Filed: September 26, 2002
    Publication date: March 20, 2003
    Applicant: NEC CORPORATION
    Inventors: Mikio Oda, Sakae Kitajo, Yuzo Shimada, Masataka Itoh, Yoshinobu Kaneyama, Masahiko Fujiwara
  • Patent number: 6492681
    Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: December 10, 2002
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Jun Koyama, Hidehito Kitakado, Masataka Itoh, Hiroyuki Ogawa
  • Patent number: 6477284
    Abstract: The present invention provides a photo-electric combined substrate comprising an electric interconnection part having an electric interconnection layer and an electric insulating layer as well as an optical waveguide part consisting of a core and a clad, where the electric insulating layer in the electric interconnection part and the optical waveguide part are made of the same material; a ceramic substrate comprising an optical device and an electric device where a ceramic substrate has a concave where the concave is filled with a resin, and where at least an optical device is mounted on the ceramic substrate while an electric device on the resin in the substrate concave; and an optical waveguide comprising a core and a clad having a refractive index lower than that of the core, where the core is made of a fluorene-unit-containing epoxy acrylate resin.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: November 5, 2002
    Assignee: NEC Corporation
    Inventors: Mikio Oda, Sakae Kitajo, Yuzo Shimada, Masataka Itoh, Yoshinobu Kaneyama, Masahiko Fujiwara
  • Patent number: 6393171
    Abstract: The integrity of a solder jointing pad, which is used to mount an optical module, is enhanced by avoiding exposure to high temperatures used in the formation of an accompanying optical wave guide. The enhanced integrity of the solder jointing pad permits a mounting solder bump to be evenly distributed on the pad, which improves mounting position characteristics. The solder jointing pads are elongated in shape and arranged in parallel and perpendicular orientation with respect to an optical transmission path in the optical module. The enhanced integrity of the solder jointing pads permits a precise amount of solder to be introduced to the pads when mounting the optical module. The optical module can then be precisely positioned simply by varying the amount of solder introduced to the solder jointing pads. The optical device can be positioned with high accuracy by taking advantage of the self-alignment action which occurs between the molten solder bumps and the solder jointing pads.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: May 21, 2002
    Assignee: NEC Corporation
    Inventors: Junichi Sasaki, Masataka Itoh, Naoki Kitamura
  • Publication number: 20020033513
    Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.
    Type: Application
    Filed: March 6, 2001
    Publication date: March 21, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hidehito Kitakado, Masataka Itoh, Hiroyuki Ogawa
  • Publication number: 20010033718
    Abstract: The integrity of a solder jointing pad, which is used to mount an optical module, is enhanced by avoiding exposure to high temperatures used in the formation of an accompanying optical wave guide. The enhanced integrity of the solder jointing pad permits a mounting solder bump to be evenly distributed on the pad, which improves mounting position characteristics. The solder jointing pads are elongated in shape and arranged in parallel and perpendicular orientation with respect to an optical transmission path in the optical module. The enhanced integrity of the solder jointing pads permits a precise amount of solder to be introduced to the pads when mounting the optical module. The optical module can then be precisely positioned simply by varying the amount of solder introduced to the solder jointing pads. The optical device can be positioned with high accuracy by taking advantage of the self-alignment action which occurs between the molten solder bumps and the solder jointing pads.
    Type: Application
    Filed: June 20, 2001
    Publication date: October 25, 2001
    Applicant: NEC Corporation
    Inventors: Junichi Sasaki, Masataka Itoh, Naoki Kitamura
  • Patent number: 6298861
    Abstract: A wig stopper including a bent, counter-bendable, component that is obtained by processing a single elastic thin sheet to bend and impart a counter-bendable characteristic thereto. The wig stopper further includes a number of hair-fastening components, each having a base end part provided on the longitudinal side of the upper end of the bent, counter-bendable, component. Also, a tip end part is extended to the longitudinal side of the lower end of the bent, counter-bendable, component such that the hair-fastening components are arranged in a comb-tooth fashion.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: October 9, 2001
    Assignee: Aderans Co., Ltd.
    Inventors: Masanori Kageyama, Masataka Itoh
  • Publication number: 20010025960
    Abstract: There is provided a semiconductor device using a TFT structure of high reliability.
    Type: Application
    Filed: May 17, 2001
    Publication date: October 4, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Shunpei Yamazaki, Masataka Itoh
  • Patent number: 6259138
    Abstract: A semiconductor device using a TFT including a multilayered gate electrode and an LDD region partially overlapping with the multilayered gate electrode via a gate insulating film is provided.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: July 10, 2001
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hisashi Ohtani, Shunpei Yamazaki, Masataka Itoh
  • Patent number: 6238100
    Abstract: A semiconductor optical amplifier is mounted on a substrate which is provided for a package. Fiber blocks in which plural parallel internal optical fibers are supported are fitted to the package. The optical fibers are optically coupled with the semiconductor optical amplifier via optical waveguides formed on the substrate. V grooves for supporting the optical fibers which protrude out from the fiber block are formed on the substrate. Positionings of the optical fibers are performed by fitting the fiber blocks to the package so that end faces of the optical fibers butt against end walls of the V grooves.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: May 29, 2001
    Assignee: NEC Corporation
    Inventors: Junichi Sasaki, Tomoaki Kato, Masataka Itoh
  • Patent number: 6115515
    Abstract: An optical device mounting board with electrodes mounted on the surface of the mounting board and separated from one another by grooves dividing the surface of the mounting board includes printed circuit boards having distribution lines for connecting the divided electrodes and spanning the grooves.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: September 5, 2000
    Assignee: NEC Corporation
    Inventors: Masataka Itoh, Junichi Sasaki