Patents by Inventor Masataka Kondo
Masataka Kondo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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ELECTRIC PULSE DECOMPOSITION METHOD, COMPOSITE MATERIAL, AND COMPOSITE MATERIAL DECOMPOSITION METHOD
Publication number: 20220323967Abstract: An electric pulse decomposition method for separating a composite material by an electric pulse, the composite material being obtained by bonding or joining a plurality of conductors to each other with an insulating member, the electric pulse decomposition method including a protrusion formation step for forming a protrusion in a specific site, on a side on which the composite material is arranged, of at least one of the plurality of conductors, and a separation step for separating the plurality of conductors in the composite material 1 by respectively bringing electrodes into contact with surfaces of the plurality of conductors and applying an electric pulse between the electrodes to destroy the insulating member. This makes it possible to separate the plurality of conductors from the composite material by making a shock wave caused by a current of the dielectric breakdown functioning as an adhesive to effectively destroy the insulating member.Type: ApplicationFiled: February 22, 2022Publication date: October 13, 2022Inventors: Satoshi OYAMA, Naoki Kishimoto, Chiharu Tokoro, Soowon Lim, Taketoshi Koita, Masataka Kondo, Takao Namihira -
Patent number: 11365758Abstract: The objective is to provide a bolt which can more effectively suppress occurrence of seizure due to both oblique insertion and biting of foreign substances. The bolt includes a tapered surface, a guide portion, and a threaded portion in order from a distal end side and further includes a plurality of recesses provided on the tapered surface and a plurality of cutout portions provided at a distal end portion of the threaded portion.Type: GrantFiled: November 30, 2017Date of Patent: June 21, 2022Assignee: MEIDOH CO., LTD.Inventors: Koji Makino, Masataka Kondo, Shungo Maki, Akihiro Futamura
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Patent number: 11209038Abstract: A bolt which can prevent seizure is provided due to the bolt being installed obliquely. A guide portion is formed between a groove portion formed at a distal end portion of the threaded portion and a surface end position on a base end side of the tapered surface, a starting end portion of the guide portion being an intersection between the surface end position on the base end side of the tapered surface and a helix according to the groove portion, a terminal end portion of the guide portion overlaps with the distal end portion of the threaded portion, an angle in the direction around the axis of the bolt from the starting end portion to the terminal end portion is set in the range of 90° to 360°.Type: GrantFiled: October 25, 2017Date of Patent: December 28, 2021Assignee: MEIDOH CO., LTD.Inventors: Koji Makino, Masataka Kondo, Katsuhide Takei, Akihiro Futamura, Shun Nishimura, Shungo Maki
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Publication number: 20190309788Abstract: The objective is to provide a bolt which can more effectively suppress occurrence of seizure due to both oblique insertion and biting of foreign substances. The bolt includes a tapered surface, a guide portion, and a threaded portion in order from a distal end side and further includes a plurality of recesses provided on the tapered surface and a plurality of cutout portions provided at a distal end portion of the threaded portion.Type: ApplicationFiled: November 30, 2017Publication date: October 10, 2019Applicant: MEIDOH CO., LTD.Inventors: Koji MAKINO, Masataka KONDO, Shungo MAKI, Akihiro FUTAMURA
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Patent number: 10434477Abstract: A fiber-reinforced porous hollow fiber membrane comprising a hollow fiber membrane and a reinforcing fiber completely or partially embedded in the hollow fiber membrane; wherein the reinforcing fiber is placed in a portion that does not exceed 90%, preferably 80%, of the thickness of the hollow fiber membrane as viewed from an inner or outer peripheral surface of the hollow fiber membrane on a side that is not a side of the porous hollow fiber membrane to come in contact with an object to be treated, and preferably at least 50 volume % of the cross section of the reinforcing fiber is embedded in the hollow fiber membrane. The obtained fiber-reinforced porous hollow fiber membrane has excellent permeability, separation performance, and mechanical properties.Type: GrantFiled: April 22, 2014Date of Patent: October 8, 2019Assignee: NOK CorporationInventors: Takatoshi Sato, Kazuhiko Namigata, Masataka Kondo
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Publication number: 20190257346Abstract: A bolt which can prevent seizure is provided due to the bolt being installed obliquely. A guide portion is formed between a groove portion formed at a distal end portion of the threaded portion and a surface end position on a base end side of the tapered surface, a starting end portion of the guide portion being an intersection between the surface end position on the base end side of the tapered surface and a helix according to the groove portion, a terminal end portion of the guide portion overlaps with the distal end portion of the threaded portion, an angle in the direction around the axis of the bolt from the starting end portion to the terminal end portion is set in the range of 90° to 360°.Type: ApplicationFiled: October 25, 2017Publication date: August 22, 2019Applicant: MEIDOH CO., LTD.Inventors: Koji MAKINO, Masataka KONDO, Katsuhide TAKEI, Akihiro FUTAMURA, Shun NISHIMURA, Shungo MAKI
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Patent number: 10150085Abstract: A membrane-forming dope for carbon membranes, comprising polyphenylene oxide in an amount giving a concentration of 15 to 40 wt. % in the membrane-forming dope, and sulfur in an amount giving a ratio of 0.1 to 5.0 wt. %, preferably 0.2 to 3.0 wt. %, of the total weight of the polyphenylene oxide and the sulfur, both of which are dissolved in a solvent that can dissolve these components. A hollow fiber carbon membrane is produced by molding the membrane-forming dope for carbon membranes in a hollow shape by means of a wet or dry-wet spinning method using a double tubular nozzle, subjecting the molded product to an infusibilization treatment by heating at 150 to 350° C. in the air, and then subjecting it to a carbonization treatment by heating at 600 to 800° C. in an inert atmosphere or under vacuum. When the product molded in a hollow shape by means of a wet or dry-wet spinning method is subjected to an infusibilization treatment by heating in the air while stretching the product with a stress of 0.002 to 0.Type: GrantFiled: October 9, 2015Date of Patent: December 11, 2018Assignee: NOK CorporationInventors: Masataka Kondo, Kensuke Watanabe, Hirokazu Yamamoto
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Publication number: 20170296978Abstract: A membrane-forming dope for carbon membranes, comprising polyphenylene oxide in an amount giving a concentration of 15 to 40 wt. % in the membrane-forming dope, and sulfur in an amount giving a ratio of 0.1 to 5.0 wt. %, preferably 0.2 to 3.0 wt. %, of the total weight of the polyphenylene oxide and the sulfur, both of which are dissolved in a solvent that can dissolve these components. A hollow fiber carbon membrane is produced by molding the membrane-forming dope for carbon membranes in a hollow shape by means of a wet or dry-wet spinning method using a double tubular nozzle, subjecting the molded product to an infusibilization treatment by heating at 150 to 350° C. in the air, and then subjecting it to a carbonization treatment by heating at 600 to 800° C. in an inert atmosphere or under vacuum. When the product molded in a hollow shape by means of a wet or dry-wet spinning method is subjected to an infusibilization treatment by heating in the air while stretching the product with a stress of 0.002 to 0.Type: ApplicationFiled: October 9, 2015Publication date: October 19, 2017Inventors: Masataka KONDO, Kensuke WATANABE, Hirokazu YAMAMOTO
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Publication number: 20160082396Abstract: A fiber-reinforced porous hollow fiber membrane comprising a hollow fiber membrane and a reinforcing fiber completely or partially embedded in the hollow fiber membrane; wherein the reinforcing fiber is placed in a portion that does not exceed 90%, preferably 80%, of the thickness of the hollow fiber membrane as viewed from an inner or outer peripheral surface of the hollow fiber membrane on a side that is not a side of the porous hollow fiber membrane to come in contact with an object to be treated, and preferably at least 50 volume % of the cross section of the reinforcing fiber is embedded in the hollow fiber membrane. The obtained fiber-reinforced porous hollow fiber membrane has excellent permeability, separation performance, and mechanical properties.Type: ApplicationFiled: April 22, 2014Publication date: March 24, 2016Inventors: Takatoshi Sato, Kazuhiko Namigata, Masataka Kondo
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Patent number: 8123601Abstract: To provide a game device capable of realizing a user interface that makes it easier for a player to realize a reference trajectory to input and a time to begin inputting of the reference trajectory. A display unit (74) displays a game screen including a moving image and a trajectory image for indicating a reference trajectory. The moving image moves from a given initial position to the start point of the reference trajectory. In the case where the moving image reaches the start point of the reference trajectory, the moving image moves along the reference trajectory. A determination unit (78) determines whether or not the position designated by a player is located within an area based on the position of the moving image during a period when the moving image is moving along the reference trajectory. A game process is carried out based on a result of determination.Type: GrantFiled: April 21, 2009Date of Patent: February 28, 2012Assignee: Konami Digital Entertainment Co., Ltd.Inventor: Masataka Kondo
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Publication number: 20090270169Abstract: To provide a game device capable of realizing a user interface that makes it easier for a player to realize a reference trajectory to input and a time to begin inputting of the reference trajectory. A display unit (74) displays a game screen including a moving image and a trajectory image for indicating a reference trajectory. The moving image moves from a given initial position to the start point of the reference trajectory. In the case where the moving image reaches the start point of the reference trajectory, the moving image moves along the reference trajectory. A determination unit (78) determines whether or not the position designated by a player is located within an area based on the position of the moving image during a period when the moving image is moving along the reference trajectory. A game process is carried out based on a result of determination.Type: ApplicationFiled: April 21, 2009Publication date: October 29, 2009Applicant: KONAMI DIGITAL ENTERTAINMENT CO., LTDInventor: Masataka KONDO
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Patent number: 6864693Abstract: A semiconductor integrated circuit is provided in which a negative voltage generation circuit capable of supplying a memory cell transistor substrate with a stable negative voltage, independently of the fluctuation of a power source voltage or environmental conditions and the process conditions etc., is realized easily, and in which the data holding time of a memory can be secured sufficiently, and the power consumption is reduced.Type: GrantFiled: May 10, 2001Date of Patent: March 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kondo, Kiyoto Ohta, Tomonori Fujimoto
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Patent number: 6628162Abstract: A semiconductor integrated circuit includes a functional circuit and a power source voltage generating circuit used for operating the functional circuit. In the power source voltage generating circuit, output stage transistors are driven by comparing a plurality of reference voltages produced by a plurality of resistors connected in series to one another with output voltages of a plurality of differential amplifiers connected in parallel to one another and varying gate voltages.Type: GrantFiled: November 16, 2001Date of Patent: September 30, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kondo, Kiyoto Ohta, Yuji Yamasaki, Toshikazu Suzuki, Masanobu Hirose
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Patent number: 6628555Abstract: A boosting circuit included in a semiconductor integrated circuit for efficiently stabilizing a boosted potential, including a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.Type: GrantFiled: August 15, 2002Date of Patent: September 30, 2003Assignee: Matsushita Electric Industrial Co. Ltd.Inventors: Masataka Kondo, Kiyoto Oota, Tomonori Fujimoto, Yoshihiko Sumimoto
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Patent number: 6506260Abstract: A method for cleaning a photovoltaic module, the photovoltaic module having a first electrode layer formed on an insulating substrate, a photovoltaic layer, and a second electrode layer. The laminate is electrically divided between a power generating region and peripheral regions by means of grooves. The power generating region is divided into a plurality of photovoltaic cells by means of laser-scribed grooves. At least some of the photovoltaic cells are connected electrically in series with one another. The cleaning method includes a process for transporting the photovoltaic module immersed in a cleaning fluid, while being kept in a horizontal position with the laminate upward as it is transported, and applying ultrasonic vibration to the cleaning fluid, thereby removing particles in the scribed grooves.Type: GrantFiled: March 22, 2000Date of Patent: January 14, 2003Assignee: Kaneka CorporationInventors: Masafumi Hiraishi, Masataka Kondo, Hideo Yamagishi, Katsuhiko Hayashi, Toshihide Okatsu
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Publication number: 20020191447Abstract: To provide a boosting circuit that is included in a semiconductor integrated circuit in order for stabilizing a boosted potential with high efficiency. Therefore, the present invention is provided with a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.Type: ApplicationFiled: August 15, 2002Publication date: December 19, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kondo, Kiyoto Oota, Tomonori Fujimoto, Yoshihiko Sumimoto
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Patent number: 6469242Abstract: In a substrate-integration-type thin-film solar cell module wherein an element is directly formed on a transparent insulating substrate, wiring between a bus region and a terminal box is formed of a solder-plated copper foil. To ensure insulation between a device surface and the solder-plated copper foil, an insulating sheet buried in a filler is inserted in a gap therebetween. A glass nonwoven fabric sheet or a 160° C.-heat-resistant synthetic fiber fabric sheet can be used for the insulating sheet. Contact between an edge of an opening in a back protection cover and the wiring is prevented by positioning output wiring by means of an insulating sheet portion. An insulating sheet for preventing entrance of water from the opening is disposed at the opening.Type: GrantFiled: March 2, 2000Date of Patent: October 22, 2002Assignee: Kaneka CorporationInventor: Masataka Kondo
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Patent number: 6461444Abstract: Disclosed is a method of manufacturing a semiconductor device, in which a substrate is successively transferred through a first film-forming chamber for forming a semiconductor layer of a first conductivity type, a second film-forming chamber for forming an i-type semiconductor layer, and a third film-forming chamber for forming a semiconductor layer of a second conductivity type, thereby forming successively a semiconductor layer of a first conductivity type, an i-type semiconductor layer, and a semiconductor layer of a second conductivity type on the substrate. The method comprises the step of simultaneously transferring the substrates arranged within the first, second and third film-forming chambers and each having a semiconductor layer into adjacent chambers on the downstream side.Type: GrantFiled: March 21, 2000Date of Patent: October 8, 2002Assignee: Kaneka CorporationInventors: Hitoshi Nishio, Hideo Yamagishi, Masataka Kondo
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Patent number: 6459643Abstract: A boosting circuit included in a semiconductor integrated circuit for efficiently stabilizing a boosted potential, including a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.Type: GrantFiled: February 28, 2001Date of Patent: October 1, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kondo, Kiyoto Oota, Tomonori Fujimoto, Yoshihiko Sumimoto
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Patent number: 6437231Abstract: An integrated thin-film solar battery having a plurality of unit elements connected in series includes a substrate, a plurality of spaced apart first electrode layers formed on the substrate; a plurality of semiconductor layers disposed on said plurality of first electrode layers in such a manner that each of the semiconductor layers is formed on two adjacent first electrodes and has a connection opening located on one of the two first electrodes, an electrically conductive layer formed on each of the semiconductor layers except on the region of the connection opening, and a second electrode layer disposed on each of the electrically conductive layers such that the second electrode layer is electrically connected to one of the two adjacent first electrode layers through the connection opening, to form a region interposed between the second electrode layer and the other first electrode layer as the unit element.Type: GrantFiled: May 24, 2001Date of Patent: August 20, 2002Assignee: Kanegafuchi Kagaku Kogyo Kabushiki KaishaInventors: Shinichiro Kurata, Katsuhiko Hayashi, Atsuo Ishikawa, Masataka Kondo