Patents by Inventor Masataka Minami
Masataka Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040049464Abstract: A storage-medium rental system includes a portable storage medium to be rented to the user, a portable semiconductor memory owned by the user, a rental-shop apparatus owned by the rental agent, and a reproduction apparatus owned by the user. The storage medium prestores encrypted content generated by encrypting digital work using a content encryption key. The semiconductor memory has an area for securely storing a content decryption key. The rental-shop apparatus stores a content decryption key for decrypting the encrypted content. The rental-shop apparatus writes the content decryption key to the semiconductor memory. The reproduction apparatus securely reads the content decryption key from the semiconductor memory, reads the encrypted content from the storage medium, decrypts the encrypted content using the content decryption key, and reproduces the decrypted content.Type: ApplicationFiled: September 5, 2002Publication date: March 11, 2004Inventors: Motoji Ohmori, Masataka Minami, Masaya Yamamoto
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Patent number: 6687683Abstract: A data protection system obtains data having a first content on which a first encryption has been performed and a second content on which a second encryption has been performed, the second encryption more difficult to break than the first encryption. A first content decryption unit decrypts the first content, using a first encryption method corresponding to the first encryption of the first content. A second content decryption unit decrypts the second content using a second decryption method that corresponds to the second encryption. The decrypting contents can be executed by a software, and the second content decryption unit can include one of tamperproof hardware and an apparatus that executes tamperproof software.Type: GrantFiled: October 8, 1999Date of Patent: February 3, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shunji Harada, Masayuki Kozuka, Masataka Minami, Makoto Tatebayashi
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Publication number: 20040012040Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micropatterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.Type: ApplicationFiled: June 27, 2003Publication date: January 22, 2004Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
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Patent number: 6677649Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.Type: GrantFiled: May 5, 2000Date of Patent: January 13, 2004Assignee: Hitachi, Ltd.Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
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Patent number: 6677194Abstract: A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.Type: GrantFiled: June 6, 2002Date of Patent: January 13, 2004Assignee: Hitachi, Ltd.Inventors: Toshiaki Yamanaka, Akio Nishida, Yasuko Yoshida, Shuji Ikeda, Kenichi Kuroda, Shiro Kamohara, Shinichiro Kimura, Eiichi Murakami, Hideyuki Matsuoka, Masataka Minami
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Patent number: 6661746Abstract: The recording medium of this invention is recorded with a plurality of digital data and a plurality of reproduction path information defining a reproduction order of the plurality of digital data, wherein the plurality of reproduction path information includes first reproduction path information defining a reproduction order of all of the plurality of digital data recorded on the recording medium and second reproduction path information defining a reproduction order of at least one of the plurality of digital data recorded on the recording medium.Type: GrantFiled: November 30, 2001Date of Patent: December 9, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Tagawa, Masataka Minami, Masayuki Kozuka
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Publication number: 20030221103Abstract: A semiconductor memory card comprising a control IC 302, a flash memory 303, and a ROM 304. The ROM 304 holds information such as a medium ID 341 unique to the semiconductor memory card. The flash memory 303 includes an authentication memory 332 and a non-authentication memory 331. The authentication memory 332 can be accessed only by external devices which have been affirmatively authenticated. The non-authentication memory 331 can be accessed by external devices whether the external devices have been affirmatively authenticated or not. The control IC 302 includes control units 325 and 326, an authentication unit 321 and the like. The control units 325 and 326 control accesses to the authentication memory 332 and the non-authentication memory 331, respectively. The authentication unit 321 executes a mutual authentication with an external device.Type: ApplicationFiled: June 13, 2003Publication date: November 27, 2003Inventors: Teruto Hirota, Makoto Tatebayashi, Taihei Yugawa, Masataka Minami, Masayuki Kozuka
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Publication number: 20030174593Abstract: The recording medium of this invention is recorded with a plurality of digital data and a plurality of reproduction path information defining a reproduction order of the plurality of digital data, wherein the plurality of reproduction path information includes first reproduction path information defining a reproduction order of all of the plurality of digital data recorded on the recording medium and second reproduction path information defining a reproduction order of at least one of the plurality of digital data recorded on the recording medium.Type: ApplicationFiled: March 11, 2003Publication date: September 18, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Tagawa, Masataka Minami, Masayuki Kozuka
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Patent number: 6606707Abstract: A semiconductor memory card comprising a control IC 302, a flash memory 303, and a ROM 304. The ROM 304 holds information such as a medium ID 341 unique to the semiconductor memory card. The flash memory 303 includes an authentication memory 332 and a non-authentication memory 331. The authentication memory 332 can be accessed only by external devices which have been affirmatively authenticated. The non-authentication memory 331 can be accessed by external devices whether the external devices have been affirmatively authenticated or not. The control IC 302 includes control units 325 and 326, an authentication unit 321 and the like. The control units 325 and 326 control accesses to the authentication memory 332 and the non-authentication memory 331, respectively. The authentication unit 321 executes a mutual authentication with an external device.Type: GrantFiled: April 24, 2000Date of Patent: August 12, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Teruto Hirota, Makoto Tatebayashi, Taihei Yugawa, Masataka Minami, Masayuki Kozuka
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Patent number: 6529506Abstract: A data processing apparatus is provided with a data obtaining unit which receives a network signal sn on a network N and obtains distributed audio data Dau in which copyright information or the like is embedded, and a control unit which obtains information indicating a watermarking method which has been used when embedding the copyright information or the like in the audio data. The embedded information is extracted by an appropriate watermarking method according to the obtained information indicating the used watermarking method. The extracted information is again embedded in the distributed audio data Dau by using a predetermined watermarking method, and thus obtained audio data is recorded on a recording medium.Type: GrantFiled: October 8, 1999Date of Patent: March 4, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masaya Yamamoto, Tomoyuki Nonomura, Masataka Minami, Masayuki Kozuka
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Publication number: 20020187596Abstract: A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.Type: ApplicationFiled: June 6, 2002Publication date: December 12, 2002Applicant: Hitachi, Ltd.Inventors: Toshiaki Yamanaka, Akio Nishida, Yasuko Yoshida, Shuji Ikeda, Kenichi Kuroda, Shiro Kamohara, Shinichiro Kimura, Eiichi Murakami, Hideyuki Matsuoka, Masataka Minami
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Patent number: 6466735Abstract: The car navigation file of the optical disk stores data which is used for navigating the car, and the video title set stores a plurality of video titles concerning facilities located in districts included in the map data. A VOB comprising one scene of a video image of a video title is a filmed shot in high picture quality. The VOB includes a writing command that position information of a position associated with the video information be written in the rewitable area when the predetermined operation is performed during the reproduction of the optical disk. When the disk reproduction apparatus executes the writing command, the position information can be written in the rewritable area. Consequently, the user can easily have the destination written in the optical disk, enjoying the filmed shots.Type: GrantFiled: September 16, 1998Date of Patent: October 15, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masayuki Kozuka, Masataka Minami, Kazuoki Otani, Osamu Kawashima, Yoshihisa Fukushima, Yoshiho Gotoh
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Publication number: 20020140456Abstract: A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner thatType: ApplicationFiled: May 28, 2002Publication date: October 3, 2002Inventors: Hiroyuki Mizuno, Masataka Minami, Koichiro Ishibashi, Masayuki Miyazaki
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Publication number: 20020129235Abstract: An object of the invention is to provide a system in which various services can be received by a plurality of receiving devices having different structures, without having to take into consideration the difference in the structures, by connecting an adapter that corresponds to the service the user wishes to receive. The distribution server 301 communicates with the storage media access adapter 303 via the receiving device 302, and thereby controls distribution of digital data.Type: ApplicationFiled: January 11, 2001Publication date: September 12, 2002Inventors: Ryuichi Okamoto, Masayuki Kozuka, Mitsuhiro Inoue, Masataka Minami
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Publication number: 20020117722Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.Type: ApplicationFiled: May 5, 2000Publication date: August 29, 2002Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
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Publication number: 20020091643Abstract: An object of the invention is to provide a digital data distribution system in which profits can be properly allocated to digital data provider companies and right holders of digital data, where the digital data distribution system offers subscription services.Type: ApplicationFiled: January 11, 2001Publication date: July 11, 2002Inventors: Ryuichi Okamoto, Masayuki Kozuka, Mitsuhiro Inoue, Masataka Minami
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Publication number: 20020073102Abstract: The distribution server administers downloading of contents and writing in storage media.Type: ApplicationFiled: December 8, 2000Publication date: June 13, 2002Inventors: Ryuichi Okamoto, Masayuki Kozuka, Masataka Minami, Mitsuhiro Inoue
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Patent number: 6404232Abstract: A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner thatType: GrantFiled: October 26, 2000Date of Patent: June 11, 2002Assignee: Hitachi, Ltd.Inventors: Hiroyuki Mizuno, Masataka Minami, Koichiro Ishibashi
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Publication number: 20020034130Abstract: The recording medium of this invention is recorded with a plurality of digital data and a plurality of reproduction path information defining a reproduction order of the plurality of digital data, wherein the plurality of reproduction path information includes first reproduction path information defining a reproduction order of all of the plurality of digital data recorded on the recording medium and second reproduction path information defining a reproduction order of at least one of the plurality of digital data recorded on the recording medium.Type: ApplicationFiled: November 30, 2001Publication date: March 21, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Tagawa, Masataka Minami, Masayuki Kozuka
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Patent number: 6351442Abstract: The recording medium of this invention is recorded with a plurality of digital data and a plurality of reproduction path information defining a reproduction order of the plurality of digital data, wherein the plurality of reproduction path information includes first reproduction path information defining a reproduction order of all of the plurality of digital data recorded on the recording medium and second reproduction path information defining a reproduction order of at least one of the plurality of digital data recorded on the recording medium.Type: GrantFiled: June 1, 1999Date of Patent: February 26, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Tagawa, Masataka Minami, Masayuki Kozuka