Patents by Inventor Masatake Nakano
Masatake Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11056381Abstract: A method for producing a bonded SOI wafer by bonding a bond wafer and a base wafer, each being formed of a silicon single crystal, together with a silicon oxide film placed therebetween, the method including: preparing, as the base wafer, a silicon single crystal wafer whose resistivity is 100 ?·cm or more and initial interstitial oxygen concentration is 10 ppma or less; forming, on the front surface of the base wafer, a silicon oxide film by performing, on the base wafer, heat treatment in an oxidizing atmosphere at a temperature of 700° C. or higher and 1000° C. or lower for 5 hours or more; bonding the base wafer and the bond wafer together with the silicon oxide film placed therebetween; and thinning the bonded bond wafer to form an SOI layer.Type: GrantFiled: August 22, 2016Date of Patent: July 6, 2021Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Toru Ishizuka, Masatake Nakano
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Patent number: 10460983Abstract: A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick.Type: GrantFiled: March 4, 2015Date of Patent: October 29, 2019Assignee: SHIN-ETSU HANDOTAI CO.,LTD.Inventors: Taishi Wakabayashi, Kenji Meguro, Masatake Nakano, Shinichiro Yagi, Tomosuke Yoshida
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Patent number: 10424484Abstract: Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.Type: GrantFiled: January 7, 2016Date of Patent: September 24, 2019Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Toru Ishizuka, Norihiro Kobayashi, Masatake Nakano
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Publication number: 20180247860Abstract: A method for producing a bonded SOI wafer by bonding a bond wafer and a base wafer, each being formed of a silicon single crystal, together with a silicon oxide film placed therebetween, the method including: preparing, as the base wafer, a silicon single crystal wafer whose resistivity is 100 ?·cm or more and initial interstitial oxygen concentration is 10 ppma or less; forming, on the front surface of the base wafer, a silicon oxide film by performing, on the base wafer, heat treatment in an oxidizing atmosphere at a temperature of 700° C. or higher and 1000° C. or lower for 5 hours or more; bonding the base wafer and the bond wafer together with the silicon oxide film placed therebetween; and thinning the bonded bond wafer to form an SOI layer.Type: ApplicationFiled: August 22, 2016Publication date: August 30, 2018Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Toru ISHIZUKA, Masatake NAKANO
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Publication number: 20170345663Abstract: Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.Type: ApplicationFiled: January 7, 2016Publication date: November 30, 2017Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Toru ISHIZUKA, Norihiro KOBAYASHI, Masatake NAKANO
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Publication number: 20170040210Abstract: A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick.Type: ApplicationFiled: March 4, 2015Publication date: February 9, 2017Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Taishi WAKABAYASHI, Kenji MEGURO, Masatake NAKANO, Shinichiro YAGI, Tomosuke YOSHIDA
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Patent number: 8466538Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.Type: GrantFiled: February 19, 2009Date of Patent: June 18, 2013Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
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Publication number: 20100314722Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.Type: ApplicationFiled: February 19, 2009Publication date: December 16, 2010Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
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Patent number: 7565186Abstract: An outer display is provided in an area exposed to the outside, of a first movable part in a closed condition where the first and second movable parts are opposed to each other. An outer operation section is provided in an area other than the exposed area of the first and second movable parts whichever comes behind the outer display in a closed condition where the first and second movable parts are opposed to each other. The operator can enter predetermined information on a predetermined display content displayed on the outer display. Even in a condition where the first and second movable parts fold closed, the operator can enter predetermined information from the outer operation section while watching the outer display, which enhances the operability.Type: GrantFiled: January 28, 2008Date of Patent: July 21, 2009Assignee: Sharp Kabushiki KaishaInventors: Kazutaka Okuzako, Masatake Nakano
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Patent number: 7531425Abstract: This invention relates to a method of fabricating a bonded wafer 39 in which a bond wafer 31 and a base wafer 32, both of which are composed of silicon single crystal, are bonded while placing an oxide film 33 in between, and the bond wafer 31 is thinned. Use of modified chemically-etched wafers as both of the bond wafer 31 and base wafer 32 is successful in reducing an unbonded area UA therebetween after annealing for bonding, where the modified chemically-etched wafer refers to a wafer which is etched by alkali etching and succeeding acid etching, while setting etching amount larger in the alkali etching than in the acid etching.Type: GrantFiled: November 19, 2002Date of Patent: May 12, 2009Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Masatake Nakano, Shinichi Tomizawa, Kiyoshi Mitani
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Publication number: 20080220821Abstract: An outer display is provided in an area exposed to the outside, of a first movable part in a closed condition where the first and second movable parts are opposed to each other. An outer operation section is provided in an area other than the exposed area of the first and second movable parts whichever comes behind the outer display in a closed condition where the first and second movable parts are opposed to each other. The operator can enter predetermined information on a predetermined display content displayed on the outer display. Even in a condition where the first and second movable parts fold closed, the operator can enter predetermined information from the outer operation section while watching the outer display, which enhances the operability.Type: ApplicationFiled: January 28, 2008Publication date: September 11, 2008Inventors: Kazutaka OKUZAKO, Masatake NAKANO
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Patent number: 7359740Abstract: An outer display is provided in an area exposed to the outside, of a first movable part in a closed condition where the first and second movable parts are opposed to each other. An outer operation section is provided in an area other than the exposed area of the first and second movable parts whichever comes behind the outer display in a closed condition where the first and second movable parts are opposed to each other. The operator can enter predetermined information on a predetermined display content displayed on the outer display. Even in a condition where the first and second movable parts fold closed, the operator can enter predetermined information from the outer operation section while watching the outer display, which enhances the operability.Type: GrantFiled: August 1, 2003Date of Patent: April 15, 2008Assignee: Sharp Kabushiki KaishaInventors: Kazutaka Okuzako, Masatake Nakano
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Patent number: 7186628Abstract: When an SOI wafer is produced by using a bond wafer made of silicon single crystal to form an SOI layer and a base wafer made of silicon single crystal to be a support substrate, one silicon wafer selected from a group consisting of an epitaxial wafer, an FZ wafer, a nitrogen doped wafer, a hydrogen annealed wafer, an intrinsic gettering wafer, a nitrogen doped and annealed wafer, and an entire N-region wafer is used as the bond wafer. Thereby, even where a thin insulator film or a thin SOI layer is formed in the SOI wafer, COPs are hardly detected in inspection of the SOI layer after the SOI wafer was completed, and a high quality SOI wafer is provided.Type: GrantFiled: January 7, 2003Date of Patent: March 6, 2007Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Masatake Nakano
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Publication number: 20060152600Abstract: A mobile phone generates respective thumbnail image data of a plurality of original image data obtained by a user in an image pickup unit with a continuous photographing form, and temporarily stores in a first memory together with the original image data. The mobile phone then displays an overview of the thumbnail image data on a display unit and, immediately thereafter, can continuously display the plurality of original image data on the display unit. The user can determine whether to store the data or not corresponding to a state of playback thereof. When the user directs to store the original image data, the original image data is permanently stored in a second memory.Type: ApplicationFiled: March 23, 2004Publication date: July 13, 2006Inventors: Hiroaki Hamada, Masatake Nakano
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Patent number: 6959854Abstract: There is provided a method for producing a bonded substrate comprising, at least, a process of joining two substrates and a process of subjecting the joined substrates to heat treatment to bond them firmly, wherein, at least, a process of cleaning for removing contaminants on the surface of the substrates is performed before joining the substrates, and then a process of drying the cleaned surface of the substrates is performed without using the water displacing method for the drying process, so that moisture is left on the substrates before joining to increase a joining strength after joining the substrates. Thereby, there can be provided a method for producing a bonded substrate wherein a joining strength of the joining interface of the substrates to be joined is improved, and thus the bonded substrate wherein there is no void failure and blister failure in the bonding interface of a bonded substrate after bonding heat treatment can be produced at high productivity and high yield.Type: GrantFiled: April 9, 2002Date of Patent: November 1, 2005Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Isao Yokokawa, Masatake Nakano, Kiyoshi Mitani
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Patent number: 6900113Abstract: The present invention provides a method for producing a bonded wafer comprising at least an ion implantation process where at least either hydrogen ions or rare gas ions are implanted into a first wafer from its surface to form a micro bubble layer (implanted layer) in the first wafer, a bonding process where the surface subjected to the ion implantation of the first wafer is bonded to a surface of a second wafer, and a delamination process where the first wafer is delaminated at the micro bubble layer, wherein the ion implantation process is performed in divided multiple steps, and a bonded wafer. Thus, there are provided a method for producing a bonded wafer, which is for reducing micro-voids generated in the ion implantation and delamination method and a bonded wafer free from micro-voids.Type: GrantFiled: May 29, 2001Date of Patent: May 31, 2005Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Masatake Nakano, Isao Yokokawa, Kiyoshi Mitani
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Publication number: 20050032331Abstract: When an SOI wafer is produced by using a bond wafer made of silicon single crystal to form an SOI layer and a base wafer made of silicon single crystal to be a support substrate, one silicon wafer selected from a group consisting of an epitaxial wafer, an FZ wafer, a nitrogen doped wafer, a hydrogen annealed wafer, an intrinsic gettering wafer, a nitrogen doped and annealed wafer, and an entire N-region wafer is used as the bond wafer. Thereby, even where a thin insulator film or a thin SOI layer is formed in the SOI wafer, COPs are hardly detected in inspection of the SOI layer after the SOI wafer was completed, and a high quality SOI wafer is provided.Type: ApplicationFiled: January 7, 2003Publication date: February 10, 2005Inventor: Masatake Nakano
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Publication number: 20050020030Abstract: This invention relates to a method of fabricating a bonded wafer 39 in which a bond wafer 31 and a base wafer 32, both of which are composed of silicon single crystal, are bonded while placing an oxide film 33 in between, and the bond wafer 31 is thinned. Use of modified chemically-etched wafers as both of the bond wafer 31 and base wafer 32 is successful in reducing an unbonded area UA therebetween after annealing for bonding, where the modified chemically-etched wafer refers to a wafer which is etched by alkali etching and succeeding acid etching, while setting etching amount larger in the alkali etching than in the acid etching.Type: ApplicationFiled: November 19, 2002Publication date: January 27, 2005Inventors: Masatake Nakano, Shinichi Tomizawa, Koyoshi Mitani
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Patent number: 6797632Abstract: In a method for producing a bonding wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating them at the micro bubble layer as a border, a peripheral portion of a thin film formed on the base wafer is removed after the delamination step. Preferably, a region of 1-5 mm from the peripheral end of the base wafer is removed. In the production of a bonding wafer by the hydrogen ion delamination method, there can be provided a bonding wafer free from problems such as generation of particles from peripheral portion of the wafer and generation of cracks in the SOI layer.Type: GrantFiled: June 7, 2001Date of Patent: September 28, 2004Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Masatake Nakano, Kiyoshi Mitani, Shinichi Tomizawa
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Publication number: 20040116167Abstract: An outer display is provided in an area exposed to the outside, of a first movable part in a closed condition where the first and second movable parts are opposed to each other. An outer operation section is provided in an area other than the exposed area of the first and second movable parts whichever comes behind the outer display in a closed condition where the first and second movable parts are opposed to each other. The operator can enter predetermined information on a predetermined display content displayed on the outer display. Even in a condition where the first and second movable parts fold closed, the operator can enter predetermined information from the outer operation section while watching the outer display, which enhances the operability.Type: ApplicationFiled: August 1, 2003Publication date: June 17, 2004Inventors: Kazutaka Okuzako, Masatake Nakano