Patents by Inventor Masatake Nakano

Masatake Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6720640
    Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: April 13, 2004
    Assignees: Shin-Etsu Handotai Co., Ltd., S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Susumu Kuwabara, Kiyoshi Mitani, Naoto Tate, Masatake Nakano, Thierry Barge, Christophe Maleville
  • Publication number: 20040035525
    Abstract: There is provided a method for producing a bonded substrate comprising, at least, a process of joining two substrates and a process of subjecting the joined substrates to heat treatment to bond them firmly, wherein, at least, a process of cleaning for removing contaminants on the surface of the substrates is performed before joining the substrates, and then a process of drying the cleaned surface of the substrates is performed without using the water displacing method for the drying process, so that moisture is left on the substrates before joining to increase a joining strength after joining the substrates. Thereby, there can be provided a method for producing a bonded substrate wherein a joining strength of the joining interface of the substrates to be joined is improved, and thus the bonded substrate wherein there is no void failure and blister failure in the bonding interface of a bonded substrate after bonding heat treatment can be produced at high productivity and high yield.
    Type: Application
    Filed: December 16, 2002
    Publication date: February 26, 2004
    Inventors: Isao Yokokawa, Masatake Nakano, Kiyoshi Mitani
  • Publication number: 20030219957
    Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.
    Type: Application
    Filed: May 29, 2003
    Publication date: November 27, 2003
    Applicants: Shin-Etsu Handotai Co., Ltd., S. O. I. Tec Silicon on Insulator Technologies
    Inventors: Susumu Kuwabara, Kiyoshi Mitani, Naoto Tate, Masatake Nakano, Thierry Barge, Christophe Maleville
  • Publication number: 20030153162
    Abstract: The present invention provides a method for producing a bonded wafer comprising at least an ion implantation process where at least either hydrogen ions or rare gas ions are implanted into a first wafer from its surface to form a micro bubble layer (implanted layer) in the first wafer, a bonding process where the surface subjected to the ion implantation of the first wafer is bonded to a surface of a second wafer, and a delamination process where the first wafer is delaminated at the micro bubble layer, wherein the ion implantation process is performed in divided multiple steps, and a bonded wafer. Thus, there are provided a method for producing a bonded wafer, which is for reducing micro-voids generated in the ion implantation and delamination method and a bonded wafer free from micro-voids.
    Type: Application
    Filed: November 26, 2002
    Publication date: August 14, 2003
    Inventors: Masatake Nakano, Isao Yokokawa, Kiyoshi Mitani
  • Patent number: 6596610
    Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: July 22, 2003
    Assignees: Shin-Etsu Handotai Co. Ltd., S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Susumu Kuwabara, Kiyoshi Mitani, Naoto Tate, Masatake Nakano, Thierry Barge, Christophe Maleville
  • Patent number: 6534384
    Abstract: A method for manufacturing an SOI wafer. The method includes forming an oxide film on a surface of at least one silicon wafer of two silicon wafers. The method also includes bonding the silicon wafers through the oxide film at room temperature to form a room temperature bond end, one of the two silicon wafers being a bond wafer. The method further includes heat treating the wafers in an oxidizing atmosphere to form a heat treatment bond end. Thereafter, an outer periphery of the bond wafer is removed from an outer peripheral edge of the bond wafer up to a region between the room temperature bond end and the heat treatment bond end. The thickness of the bond wafer is reduced to form an SOI layer.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: March 18, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masatake Nakano, Katsuo Yoshizawa
  • Publication number: 20010055863
    Abstract: The object of the invention is to reduce an outer circumferential edge removing width of the SOI wafer when a bonded SOI wafer is made and prevent deposition of polysilicon at the outer circumference of the SOI layer when an epitaxial layer is grown. An SOI layer is formed by the steps of forming an oxide film on a surface of at least one silicon wafer of two silicon wafers, bonding the other silicon wafer through said oxide film at a room temperature, the wafers are heat treated in oxidizing atmosphere, thereafter an outer periphery of a bond wafer is removed from an outer peripheral edge of the bond wafer up to a region between bonding ends through bonding at a room temperature and heat treatment bonding ends and making the bond wafer into a thin film of desired thickness.
    Type: Application
    Filed: June 3, 1999
    Publication date: December 27, 2001
    Inventors: MASATAKE NAKANO, KATSUO YOSHIZAWA
  • Patent number: 6239004
    Abstract: In a method of fabricating a bonded wafer, an oxide film is first formed on the surface of at least one of two mirror-polished silicon wafers. The two silicon wafers are superposed such that the mirror-polished surfaces come into close contact with each other, and heat treatment is performed in order to join the wafers together firmly. Subsequently, the thickness of one of the wafers is reduced so as to yield a thin film, the surface of which is then polished and subjected to vapor-phase etching in order to make the thickness of the thin film uniform. Optionally, the vapor-phase-etched surface is then mirror-polished. The surface of the bonded wafer is oxidized, and the generated surface oxide film is then removed. In the method, the thickness of the oxide film formed on the surface of the bonded wafer is made not greater than 50 nm.
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: May 29, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Kiyoshi Mitani, Masatake Nakano
  • Patent number: 6004866
    Abstract: A method for manufacturing a bonded wafer comprises the steps of; mirror-polishing a surface of first and second substrates, bringing the mirror-polished surfaces of the substrates contact with each other to join them, and subjecting the substrates to a heat treatment to firmly bond them. One of the surfaces of the first and second substrates prior to bonding, or one surface of the bonded wafer is subjected to a polishing treatment for exerting little influence by irregularities on a rear surface of the one substrate or by a figure of a surface of a polishing plate which is in contact with the rear surface of the one substrate.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: December 21, 1999
    Assignee: Shin-Etsu Handotai, Co., Ltd.
    Inventors: Masatake Nakano, Kiyoshi Mitani, Masahiro Sakai
  • Patent number: 5427052
    Abstract: A method and apparatus for uniformizing a bonded SOI (silicon on insulator) thin film layer by the reaction of chemical vapor-phase corrosion excited by the ultraviolet light, which effect the measurement of film thickness efficiently and conveniently and consequently attaining highly accurate control of the dispersion of thickness of the thin film layer without requiring the substrate to be removed from the reaction vessel for chemical vapor-phase corrosion on each occasion of the measurement or necessitating installation of a mechanism for alteration of the position of measurement inside or outside the reaction vessel are disclosed. The measurement of film thickness is carried out by keeping observation of interference fringes due to distribution of thickness of the film layer.
    Type: Grant
    Filed: April 27, 1992
    Date of Patent: June 27, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Masatake Nakano, Masatake Katayama, Takao Abe
  • Patent number: 5376215
    Abstract: A method and apparatus for uniformizing a bonded SOI (silicon on insulator) thin film layer by the reaction of chemical vapor-phase corrosion excited by the ultraviolet light, which effect the measurement of film thickness efficiently and conveniently and consequently attaining highly accurate control of the dispersion of thickness of the thin film layer without requiring the substrate to be removed from the reaction vessel for chemical vapor-phase corrosion on each occasion of the measurement or necessitating installation of a mechanism for alteration of the position of measurement inside or outside the reaction vessel are disclosed. The measurement of film thickness is carried out by keeping observation of interference fringes due to distribution of thickness of the film layer.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: December 27, 1994
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Masatake Nakano, Masatake Katayama, Takao Abe
  • Patent number: 5240883
    Abstract: A thin Silicon film On Insulator (SOI) material fabricating method which is capable of providing a very high thickness uniformity of the silicon film, a process simplification and a considerable reduction of processing cost is disclosed, in which a silicon oxide film is formed on one or both of a p-type silicon bond wafer and a silicon base wafer, then the two wafers are bonded together through the silicon oxide film, subsequently a fixed positive charge is induced in the silicon oxide film to form a n-type inversion layer in the p-type silicon bond wafer adjacent to an interface between the p-type silicon bond wafer and the silicon oxide film layer, and thereafter a chemical etching is effected while applying a positive voltage to the p-type silicon bond wafer so that an etch-stop is made at an interface between a depletion layer including the n-type inversion layer and the p-type layer.
    Type: Grant
    Filed: February 25, 1992
    Date of Patent: August 31, 1993
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takao Abe, Masatake Katayama, Akio Kanai, Konomu Ohki, Masatake Nakano