Patents by Inventor Masato Hamamoto
Masato Hamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230080620Abstract: Provided is an aluminum nitride powder useful as a raw material when an aluminum nitride sintered body excellent as an insulating high thermal conductive member is manufactured, particularly, by press molding. An aluminum nitride powder includes particles having a sphericity of 0.8 or more, in which a median size D50 obtained by a laser diffraction method is 0.5 to 1.5 ?m, a ratio D90/D50 of a particle size D90 corresponding to a cumulative undersize distribution of 90% to the D50 is 2.2 or less, a BET specific surface area is 2 to 4 m2/g, and a total oxygen concentration is 0.6 to 1.2% by mass.Type: ApplicationFiled: February 4, 2021Publication date: March 16, 2023Inventors: Yoshinori Tagashira, Yoshiaki Yamashita, Masato Hamamoto
-
Patent number: 7576406Abstract: A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.Type: GrantFiled: February 9, 2004Date of Patent: August 18, 2009Assignee: Hitachi, Ltd.Inventors: Yoichi Tamaki, Hideaki Nonami, Masato Hamamoto
-
Patent number: 6937068Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.Type: GrantFiled: August 18, 2003Date of Patent: August 30, 2005Assignee: Hitachi, Ltd.Inventors: Michiaki Nakayama, Masato Hamamoto, Kazutaka Mori, Satoru Isomura
-
Patent number: 6922803Abstract: A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns.Type: GrantFiled: March 20, 2001Date of Patent: July 26, 2005Assignees: Hitachi, Ltd., Hitachi Information Technology Co., Ltd.Inventors: Michinobu Nakao, Kazumi Hatayama, Koichiro Natsume, Yoshikazu Kiyoshige, Masaki Kouno, Masato Hamamoto, Hidefumi Yoshida, Tomoji Nakamura
-
Publication number: 20040183159Abstract: A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.Type: ApplicationFiled: February 9, 2004Publication date: September 23, 2004Applicant: Hitachi, Ltd.Inventors: Yoichi Tamaki, Hideaki Nonami, Masato Hamamoto
-
Publication number: 20040036497Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.Type: ApplicationFiled: August 18, 2003Publication date: February 26, 2004Inventors: Michiaki Nakayama, Masato Hamamoto, Kazutaka Mori, Satoru Isomura
-
Patent number: 6670201Abstract: A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.Type: GrantFiled: August 28, 2001Date of Patent: December 30, 2003Assignee: Hitachi, Ltd.Inventors: Masaki Kouno, Masato Hamamoto, Atsushi Wakahara, Hideyuki Takahashi, Keiichi Higeta, Mitsugu Kusunoki, Kazutaka Mori
-
Patent number: 6636075Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.Type: GrantFiled: February 1, 2002Date of Patent: October 21, 2003Assignee: Hitachi, Ltd.Inventors: Michiaki Nakayama, Masato Hamamoto, Kazutaka Mori, Satoru Isomura
-
Publication number: 20020073373Abstract: A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns.Type: ApplicationFiled: March 20, 2001Publication date: June 13, 2002Inventors: Michinobu Nakao, Kazumi Hatayama, Koichiro Natsume, Yoshikazu Kiyoshige, Masaki Kouno, Masato Hamamoto, Hidefumi Yoshida, Tomoji Nakamura
-
Publication number: 20020070760Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.Type: ApplicationFiled: February 1, 2002Publication date: June 13, 2002Inventors: Michiaki Nakayama, Masato Hamamoto, Kazutaka Mori, Satoru Isomura
-
Publication number: 20020036534Abstract: A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.Type: ApplicationFiled: August 28, 2001Publication date: March 28, 2002Applicant: Hitachi, Ltd.Inventors: Masaki Kouno, Masato Hamamoto, Atsushi Wakahara, Hideyuki Takahashi, Keiichi Higeta, Mitsugu Kusunoki, Kazutaka Mori
-
Patent number: 6359472Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.Type: GrantFiled: February 26, 2001Date of Patent: March 19, 2002Assignee: Hitachi, Ltd.Inventors: Michiaki Nakayama, Masato Hamamoto, Kazutaka Mori, Satoru Isomura
-
Publication number: 20010009383Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.Type: ApplicationFiled: February 26, 2001Publication date: July 26, 2001Inventors: Michiaki Nakayama, Masato Hamamoto, Kazutaka Mori, Satoru Isomura
-
Patent number: 6194915Abstract: To provide a semiconductor integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which one transistor Tp for constituting the CMOS circuit is set, with a first power-supply-voltage line Vdd through a switching transistor Tps, and electrically connecting a p-type well 3 in which the other transistor Tn for constituting the CMOS circuit is set with a second power-supply-voltage line Vss through a switching transistor Tns. Moreover, the semiconductor integrated circuit is constituted so that thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying a potential suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit is being tested.Type: GrantFiled: June 4, 1998Date of Patent: February 27, 2001Assignee: Hitachi, Ltd.Inventors: Michiaki Nakayama, Masato Hamamoto, Kazutaka Mori, Satoru Isomura
-
Patent number: 5298802Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.Type: GrantFiled: May 3, 1993Date of Patent: March 29, 1994Assignee: Hitachi, Ltd.Inventors: Mitsuo Usami, Noboru Shiozawa, Toshio Yamada, Hiromasa Katoh, Kazuyoshi Satoh, Tohru Kobayashi, Tatsuya Kimura, Masato Hamamoto, Atsushi Shimizu, Kaoru Koyu
-
Patent number: 5283480Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.Type: GrantFiled: July 25, 1990Date of Patent: February 1, 1994Assignee: Hitachi, Ltd.Inventors: Mitsuo Usami, Noboru Shiozawa, Toshio Yamada, Hiromasa Katoh, Kazuyoshi Satoh, Tohru Kobayashi, Tatsuya Kimura, Masato Hamamoto, Atsushi Shimizu, Kaoru Koyu
-
Patent number: 5140184Abstract: Dummy power source wirings connected to a power source wiring are arranged in empty regions among the signal wirings that cross the clock wirings, the dummy power source wirings being arranged over or under the clock wirings in a manner to cross the clock wirings. The dummy power source wirings are formed to equalize the capacitances of the wirings whose lengths should be equalized among, for example, the clock distributing circuits or among the clock drivers.Type: GrantFiled: November 20, 1990Date of Patent: August 18, 1992Assignee: Hitachi, Ltd.Inventors: Masato Hamamoto, Toshio Yamada
-
Patent number: 5059819Abstract: Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.Type: GrantFiled: December 16, 1987Date of Patent: October 22, 1991Assignee: Hitachi, Ltd.Inventors: Kazuo Tanaka, Masato Hamamoto, Toshio Yamada, Tohru Kobayashi, Hiromasa Katoh
-
Patent number: 5055710Abstract: Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.Type: GrantFiled: May 9, 1990Date of Patent: October 8, 1991Assignee: Hitachi, Ltd.Inventors: Kazuo Tanaka, Masato Hamamoto, Toshio Yamada, Tohru Kobayashi, Hiromasa Katoh
-
Patent number: 5043297Abstract: A wiring method for on-chip modification of an LSI is provided to cut a portion of a wire inside of the LSI with an ion beam and connect the wire with a laser induced CVD process so that the logic is changed when developing the LSI. The method comprises the steps of cutting or connecting an LSI wire even if another wire is located above or adjacent to the LSI wire and repairing an excessively cut or connected portion. The method thus makes it possible to widen the range of a possible cutting or connection spot, thereby making any kind of repairs possible, some of which would have never been repaired by the conventional method.Type: GrantFiled: August 22, 1990Date of Patent: August 27, 1991Assignee: Hitachi, Ltd.Inventors: Katsuyoshi Suzuki, Masato Hamamoto, Takahiko Takahashi