Patents by Inventor Masato Hirano

Masato Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11741925
    Abstract: There is provided an information processing device, an information processing method, and a program that further improve skills. A load weight control unit controls generation of a load weight that becomes a load with respect to motion when a keyboard is depressed by a pianist, and a keystroke recognition unit recognizes motion of the keyboard. Then, the load weight control unit performs control of starting generation of a predetermined load weight at a timing when the keystroke recognition unit recognizes that the keyboard started to be depressed, and ending generation of the load weight at a timing when the keystroke recognition unit recognizes that the keyboard ended to be depressed and started to return. The present technology can be applied to, for example, a performance skill improvement system that evaluates and trains pianists' force sense.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 29, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Hayato Nishioka, Shinichi Furuya, Masato Hirano, Takanori Oku
  • Publication number: 20230238002
    Abstract: For example, the accuracy of voice recognition is improved. A signal processing device includes: a single speech detection unit that detects whether one channel of an input voice signal is a speech of a single speaker; a cluster information updating unit that updates cluster information based on a voice feature quantity when the input voice signal is a speech of a single speaker; a voice segment detection unit that detects a speech segment of a target speaker based on the cluster information; and a voice extraction unit that extracts only the voice signal of the target speaker from a mixed voice signal containing the voice of the target speaker.
    Type: Application
    Filed: May 28, 2021
    Publication date: July 27, 2023
    Inventor: MASATO HIRANO
  • Publication number: 20220398937
    Abstract: Provided is an information processing device including an acquisition unit that acquires subjective evaluation information from a second user about each performance performed by at least part of a body of a first user moving, a learning unit that performs machine learning on a relationship between the each performance and the corresponding subjective evaluation information and generates relationship information between the each performance and the corresponding subjective evaluation information, and a presentation unit that presents feedback information to the second user based on the relationship information.
    Type: Application
    Filed: November 2, 2020
    Publication date: December 15, 2022
    Applicant: SONY GROUP CORPORATION
    Inventors: Shinichi FURUYA, Takanori OKU, Hayato NISHIOKA, Masato HIRANO, Yukako UEMATSU, Junichirou SAKATA
  • Publication number: 20220189443
    Abstract: There is provided an information processing device, an information processing method, and a program that further improve skills. A load weight control unit controls generation of a load weight that becomes a load with respect to motion when a keyboard is depressed by a pianist, and a keystroke recognition unit recognizes motion of the keyboard. Then, the load weight control unit performs control of starting generation of a predetermined load weight at a timing when the keystroke recognition unit recognizes that the keyboard started to be depressed, and ending generation of the load weight at a timing when the keystroke recognition unit recognizes that the keyboard ended to be depressed and started to return. The present technology can be applied to, for example, a performance skill improvement system that evaluates and trains pianists' force sense.
    Type: Application
    Filed: April 9, 2020
    Publication date: June 16, 2022
    Applicant: SONY GROUP CORPORATION
    Inventors: Hayato NISHIOKA, Shinichi FURUYA, Masato HIRANO, Takanori OKU
  • Patent number: 9933739
    Abstract: A drum unit includes a photosensitive drum and a cleaning member. A scratch remaining depth measured by a scratch test of the photosensitive drum under a following Test Condition 1 is 110 nm or less. Test Condition 1 is; test environment temperature=25° C.; test environment humidity=50%; test indenter=pre-mount type Berkovich indenter; scratch direction=horizontal direction; scratch speed=20 ?m/sec; initial load=0 mN; maximum reaching load=4 mN; and load at the time of measuring the scratch remaining depth=1.9 mN.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: April 3, 2018
    Assignee: Oki Data Corporation
    Inventor: Masato Hirano
  • Publication number: 20170343945
    Abstract: A drum unit includes a photosensitive drum and a cleaning member. A scratch remaining depth measured by a scratch test of the photosensitive drum under a following Test Condition 1 is 110 nm or less. Test Condition 1 is; test environment temperature=25° C.; test environment humidity=50%; test indenter=pre-mount type Berkovich indenter; scratch direction=horizontal direction; scratch speed=20 ?m/sec; initial load=0 mN; maximum reaching load=4 mN; and load at the time of measuring the scratch remaining depth=1.9 mN.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 30, 2017
    Inventor: Masato Hirano
  • Patent number: 7667299
    Abstract: A circuit board includes a substrate including electrode patterns formed thereon, first chip components mounted on the substrate and a second chip component mounted on a side of electrodes of the first chip components opposite from the substrate. The second chip component is bonded at one electrode to an electrode of the first chip component and is also bonded at the other electrode to an electrode of the first chip component. By stacking chip components in plural stages, it is possible to mount chip components with a high density on the substrate, thereby enabling reduction of the size of the circuit board.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: February 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Masato Mori, Masato Hirano, Hiroaki Onishi, Kiyoshi Nakanishi, Akihiko Odani
  • Patent number: 7540078
    Abstract: A recycling method of wastes of an electrical appliance containing an article having a circuit soldered with parts soldered with a lead free solder. The method includes discriminating a first article having a circuit soldered with lead free parts from a second article having a circuit soldered with lead containing parts; recovering, grinding and melting each of the first and second articles to separate materials of the first article and materials of the second article; recycling reusable valuables contained in the materials of the first article and second article; and shredding a portion of the first and second article not containing the reusable valuables and burying/treating the portion at a stabilizing dumping ground or a controlled dumping ground for disposal.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: June 2, 2009
    Assignee: Panasonic Corporation
    Inventors: Kenichiro Suetsugu, Shunji Hibino, Masato Hirano, Atsushi Yamaguchi, Mikiya Nakata
  • Patent number: 7473476
    Abstract: It is possible to prevent deterioration of a soldering portion and improve strength of thermal fatigue resistance by providing barrier metal layers on at least one of lead and land to cover parent materials comprising Cu-containing materials, feeding a soldering material between the lead and the land and allowing to contact in a fused condition with barrier metal layers and solidify, and thus soldering together the lead and the land.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: January 6, 2009
    Assignee: Panasonic Corporation
    Inventors: Atsushi Yamaguchi, Kazuto Nishida, Masato Hirano
  • Patent number: 7471260
    Abstract: A semiconductor memory module formed of a mounted module (12) having a semiconductor memory device (16) and a control semiconductor device (18), a circuit board (14) which contains connection terminal (20) coupled with the control semiconductor device (18) and disposed so that it is exposed from the surface of outer case (42), and an antenna connection terminal electrode (22) disposed in the inside of outer case (42); and an antenna module (24) having a sheet board (26) which includes an antenna (28) disposed on one of the surfaces in the neighborhood of the edge along the sides, a layer (30) of magnetic substance disposed on the other surface, and an antenna terminal electrode (38) disposed on the one or the other surface. The antenna module (24) is overlaid on the mounted module (12), and the antenna connection terminal electrode (22) is connected with the antenna terminal electrode (38).
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: December 30, 2008
    Assignee: Panasonic Corporation
    Inventors: Shozo Ochi, Norihito Tsukahara, Kazuhiro Ikurumi, Hidenobu Nishikawa, Masato Hirano
  • Publication number: 20080210604
    Abstract: The disclosure provides an article having a circuit mounted with parts characterized by comprising an electronic part soldered with a lead free solder and having an identification marking indicating no inclusion of lead and an electrical appliance including the same. The present invention also provides a recycling method of wastes of the same. The present invention can offer an article having a circuit mounted with parts and an electrical appliance including the same both of which facilitate identification whether lead which is poisonous to human body is contained or not.
    Type: Application
    Filed: April 25, 2008
    Publication date: September 4, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
    Inventors: Kenichiro Suetsugu, Shunji Hibino, Masato Hirano, Atsushi Yamaguchi, Mikiya Nakata
  • Publication number: 20080111756
    Abstract: A semiconductor memory module formed of a mounted module (12) having a semiconductor memory device (16) and a control semiconductor device (18), a circuit board (14) which contains connection terminal (20) coupled with the control semiconductor device (18) and disposed so that it is exposed from the surface of outer case (42), and an antenna connection terminal electrode (22) disposed in the inside of outer case (42); and an antenna module (24) having a sheet board (26) which includes an antenna (28) disposed on one of the surfaces in the neighborhood of the edge along the sides, a layer (30) of magnetic substance disposed on the other surface, and an antenna terminal electrode (38) disposed on the one or the other surface. The antenna module (24) is overlaid on the mounted module (12), and the antenna connection terminal electrode (22) is connected with the antenna terminal electrode (38).
    Type: Application
    Filed: February 2, 2006
    Publication date: May 15, 2008
    Inventors: Shozo Ochi, Norihito Tsukahara, Kazuhiro Ikurumi, Hidenobu Nishikawa, Masato Hirano
  • Publication number: 20070164079
    Abstract: An electronic component mounting method comprising: supplying an unhardened reinforcing resin on a circuit substrate; supplying a solder paste on bond areas of the circuit substrate on which electrodes of the electronic components are to be bonded; placing the electronic components on the circuit substrate; and heating and then cooling the circuit substrate with the reinforcing resin, the solder paste, and the electronic components carried thereon. The mounting method enables mounting of components with high joint reliability, while incorporating the conventional surface mount process steps. The method may also be applied to the mounting of smaller electronic components with narrower pitch without deteriorating productivity or mounting quality.
    Type: Application
    Filed: February 24, 2005
    Publication date: July 19, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masato Mori, Hiroaki Onishi, Masato Hirano, Kazuto Nishida
  • Patent number: 7150387
    Abstract: An apparatus for mounting an electric component onto a board by means of a lead-free solder material. The apparatus of the present invention has a solder material supplying chamber in which a melt of the solder material is supplied to the board by a solder material supplying unit such that the solder material adheres to a predetermined portion of the board. The apparatus further includes a cooling chamber in which the board is cooled by a cooling unit such that the solder material adhering to the board is rapidly cooled to solidify. A conditioning chamber can also be positioned between the solder material supplying chamber and the cooling chamber. The conditioning chamber conditions the board such that the solder material adhering to the board is ensured to be a completely molten condition at least before the rapid cooling of the solder material.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: December 19, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsushi Yamaguchi, Masato Hirano, Yoshinori Sakai
  • Patent number: 6871775
    Abstract: A barrier metal layer is provided on at least one of two electrodes, with one formed on a substrate and the other connected to an electronic component, so as to coat a base material of the electrode, which base material is made of a material containing Cu. Soldering between the electrode of the electronic component and the electrode on the substrate is conducted by supplying a solder material containing Sn and Bi, contacting the solder material with the barrier metal layer while the solder material is in a molten state; and solidifying the solder material. Thereby, when the electronic component is soldered to the substrate with the solder material such as an Sn—Bi based material or an Sb—Ag based material containing Bi, the degradation of a soldering part is avoided, and thus a sufficient thermal fatigue strength of the soldering part is obtained.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: March 29, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsushi Yamaguchi, Masato Hirano
  • Publication number: 20040155097
    Abstract: Deterioration of a joining portion caused by a Cu—Zn compound layer is prevented by forming compound or alloy of Cu and Sn at the joining interface including a Cu surface to be a joining portion of a circuit board and an electronic component and then carrying out soldering by use of a soldering material containing Sn and Zn in composition.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 12, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsushi Yamaguchi, Masato Hirano
  • Publication number: 20040155336
    Abstract: It is possible to prevent deterioration of a soldering portion and improve strength of thermal fatigue resistance by providing barrier metal layers on at least one of lead and land to cover parent materials comprising Cu-containing materials, feeding a soldering material between the lead and the land and allowing to contact in a fused condition with barrier metal layers and solidify, and thus soldering together the lead and the land.
    Type: Application
    Filed: February 3, 2004
    Publication date: August 12, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsushi Yamaguchi, Kazuto Nishida, Masato Hirano
  • Publication number: 20040144829
    Abstract: There are provided a method of soldering a lead-free solder which lowers a melting point of the lead-free solder and prevents deterioration of a joining strength at a portion joined by the lead-free solder, and a joined object soldered with the use of the soldering method. The lead-free solder as an alloy of tin with no lead contained is melted, and ultrasonic vibration is acted at least either to the join object to be joined by the lead-free solder or to the lead-free solder when the molten lead-free solder is solidified. Therefore crystals of contained components in the lead-free solder are made fine and the contained components are prevented from being segregated at a joining interface of the joined object, so that the joining strength at the joining interface can be increased.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 29, 2004
    Inventors: Kazumi Matsushige, Toshihisa Horiuchi, Takashi Ikari, Kenichiro Suetsugu, Masato Hirano, Shunji Hibino, Atsushi Yamaguchi
  • Publication number: 20040056067
    Abstract: An apparatus for mounting an electric component onto a board by means of a lead-free solder material. The apparatus of the present invention has a solder material supplying chamber in which a melt of the solder material is supplied to the board by a solder material supplying unit such that the solder material adheres to a predetermined portion of the board. The apparatus further includes a cooling chamber in which the board is cooled by a cooling unit such that the solder material adhering to the board is rapidly cooled to solidify. A conditioning chamber can also be positioned between the solder material supplying chamber and the cooling chamber. The conditioning chamber conditions the board such that the solder material adhering to the board is ensured to be a completely molten condition at least before the rapid cooling of the solder material.
    Type: Application
    Filed: September 24, 2003
    Publication date: March 25, 2004
    Inventors: Atsushi Yamaguchi, Masato Hirano, Yoshinori Sakai
  • Patent number: RE44384
    Abstract: In a component mounting device in which a component is picked up and mounted on a circuit board by a suction nozzle, an amount of displacement between a center position of the suction nozzle 11 and that of the picked-up component 12 is measured, and when it is larger than a preliminarily determined value, a warning is generated indicating that the parts cassette 3 from which the component 12 has been fed is in abnormal condition, as well as the mounting action of the component 12 is stopped.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: July 23, 2013
    Assignee: Panasonic Corporation
    Inventors: Masato Hirano, Yoshinori Sakai, Tateo Nakashima