Patents by Inventor Masato Koyama

Masato Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190144770
    Abstract: A system is disclosed provided with: a slag bath that retains slag cooling water and receives slag; a slag cooling water feed line and a slag pump outlet via which the slag and the slag cooling water are pumped and fed to a slag separation device; a circulation pump that forms a water flow for pumping out the slag; a slag cooling water circulation line linking from the slag separation device to the slag bath; a reverse flow line that causes the slag cooling water dispensed from the circulation pump to flow in reverse in the slag cooling water feed line; a selective supply unit capable of selectively supplying the slag cooling water dispensed from the circulation pump to the slag cooling water circulation line and the reverse flow line; and a water supply line, one end of which is connected to the slag cooling water feed line.
    Type: Application
    Filed: June 9, 2017
    Publication date: May 16, 2019
    Applicant: Mitsubishi Hitachi Power Systems, Ltd.
    Inventors: Tomoya Hayashi, Masato Murayama, Yoshinori Koyama, Naoshige Yoshida, Yasuyuki Miyata
  • Patent number: 10153326
    Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: December 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masato Koyama, Harumi Seki, Shosuke Fujii, Hidenori Miyagawa
  • Publication number: 20160276412
    Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.
    Type: Application
    Filed: December 3, 2015
    Publication date: September 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masato KOYAMA, Harumi SEKI, Shosuke FUJII, Hidenori MIYAGAWA
  • Publication number: 20160138263
    Abstract: A damping device includes a first member to be fixed to one of the horizontal members and protruding toward the other horizontal member, a second member to be fixed to the other horizontal member having a flexural rigidity smaller than the flexural rigidity of the one horizontal member and protruding toward the one horizontal member, and attenuation means coupled to the First member and to the second member. The attenuation means is provided closer to the other horizontal member.
    Type: Application
    Filed: July 7, 2014
    Publication date: May 19, 2016
    Applicant: ASAHI KASEI HOMES CORPORATION
    Inventor: Masato KOYAMA
  • Patent number: 9112132
    Abstract: A memory device includes a first electrode, a second electrode, a third electrode, a first variable resistance layer between the first electrode and the third electrode, and a second variable resistance layer between the second electrode and the third electrode. The first, second, and third electrodes, and the first and second variable resistance layers are formed of materials that cause the first variable resistance layer to transition from a high resistance state to a low resistance state when a voltage is applied across the first and second electrodes and maintain the high resistance state when the voltage is cut off, and cause the second variable resistance layer to transition from a high resistance state to a low resistance state when the voltage is applied across the first and second electrodes and transition from the high resistance state to the low resistance state when the voltage is cut off.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: August 18, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Ishikawa, Yoshifumi Nishi, Dalsuke Matsushita, Masato Koyama
  • Patent number: 9076788
    Abstract: It is made possible to provide an insulating film that can reduce the leakage current. An insulating film includes: an amorphous oxide dielectric film containing a metal, hydrogen, and nitrogen. The nitrogen amount [N] and the hydrogen amount [H] in the oxide dielectric film satisfy the following relationship: {[N]?[H]}/2?1.0×1021 cm?3.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: July 7, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Masato Koyama
  • Publication number: 20150129948
    Abstract: It is made possible to provide an insulating film that can reduce the leakage current. An insulating film includes: an amorphous oxide dielectric film containing a metal, hydrogen, and nitrogen. The nitrogen amount [N] and the hydrogen amount [H] in the oxide dielectric film satisfy the following relationship: {[N]?[H]}/2?1.0×1021 cm?3.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 14, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Masato KOYAMA
  • Patent number: 8927404
    Abstract: It is made possible to provide an insulating film that can reduce the leakage current. An insulating film includes: an amorphous oxide dielectric film containing a metal, hydrogen, and nitrogen. The nitrogen amount [N] and the hydrogen amount [H] in the oxide dielectric film satisfy the following relationship: {[N]—[H]}/2?1.0×1021 cm?3.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Masato Koyama
  • Patent number: 8866342
    Abstract: A power converting apparatus includes a first inverter circuit including a high-voltage first DC voltage source and operated at a low frequency using Si IGBTs having a high withstand voltage exceeding 1000 V and a second inverter circuit including a low-voltage capacitor operated by high-frequency PWM using SiC MOSFETs having a low withstand voltage, wherein an AC side of the first inverter circuit is connected in series to an AC side of the second inverter circuit. The power converting apparatus outputs AC power having a prescribed voltage waveform obtained from the sum of voltages generated by the first and second inverter circuits.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: October 21, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihiko Iwata, Takeshi Oi, Masato Koyama
  • Publication number: 20140138598
    Abstract: According to one embodiment, nonvolatile memory device includes a semiconductor layer, a conductive layer and a resistance change layer. The semiconductor layer has an impurity concentration less than 1×1019 cm?3. The resistance change layer is provided between the semiconductor layer and the conductive layer. The resistance change layer includes a fixed charge. The resistance change layer is reversibly transitionable between a first state and a second state by at least one selected from a current supplied via the semiconductor layer and the conductive layer and a voltage applied via the semiconductor layer and the conductive layer. A resistance of the resistance change layer in the second state is higher than a resistance of the resistance change layer in the first state.
    Type: Application
    Filed: September 13, 2013
    Publication date: May 22, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi Haimoto, Reika Ichihara, Yuuichiro Mitani, Masato Koyama
  • Patent number: 8658999
    Abstract: According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Takao Marukame, Takayuki Ishikawa, Masato Koyama
  • Patent number: 8592924
    Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: November 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Tsuchiya, Masato Koyama
  • Publication number: 20130250656
    Abstract: A memory device includes a first electrode, a second electrode, a third electrode, a first variable resistance layer between the first electrode and the third electrode, and a second variable resistance layer between the second electrode and the third electrode. The first, second, and third electrodes, and the first and second variable resistance layers are formed of materials that cause the first variable resistance layer to transition from a high resistance state to a low resistance state when a voltage is applied across the first and second electrodes and maintain the high resistance state when the voltage is cut off, and cause the second variable resistance layer to transition from a high resistance state to a low resistance state when the voltage is applied across the first and second electrodes and transition from the high resistance state to the low resistance state when the voltage is cut off.
    Type: Application
    Filed: September 6, 2012
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki ISHIKAWA, Yoshifumi Nishi, Daisuke Matsushita, Masato Koyama
  • Publication number: 20130234088
    Abstract: According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material.
    Type: Application
    Filed: December 27, 2012
    Publication date: September 12, 2013
    Inventors: Yoshifumi Nishi, Takao Marukame, Takayuki Ishikawa, Masato Koyama
  • Patent number: 8461006
    Abstract: It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si?31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 11, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Yoshinori Tsuchiya, Seiji Inumiya
  • Patent number: 8410556
    Abstract: A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: April 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Reika Ichihara, Masato Koyama
  • Patent number: 8304304
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: November 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
  • Patent number: D736815
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 18, 2015
    Assignee: Sony Corporation
    Inventors: Makoto Niijima, Satoshi Asai, Yunha Cho, Atsushi Sakamoto, Masato Koyama
  • Patent number: RE46271
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
  • Patent number: RE47640
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama