Abstract: In an imaging system, a camera unit and a control unit are connected via a source voltage line and an image signal line. The camera unit includes: a pixel array configured to generate an accumulation signal and a reset signal; a source voltage measuring circuit configured to output a voltage value (VDDA) indicating a second source voltage in the pixel array; a reference voltage generating circuit configured to generate a reference voltage (VBGR); a plurality of AD conversion devices; and a signal transmitting unit. The control unit includes: a source voltage supply device configured to supply a first source voltage (Vout) to the source voltage line; and a signal receiving device configured to receive the image signal and the result of the second AD conversion.

Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.

Abstract: An image sensor includes: a pixel unit including pixels configured to generate a first signal corresponding to an amount of received light, and output the first signal; an AD converter configured to convert the first signal into a digital second signal by performing AD conversion processing for the first signal, and output the second signal; a transmitter/receiver configured to transmit and receive, in a time division manner, transmission data including at least the second signal in a first period, and reception data input from an outside in a second period; and a first generator configured to generate a first clock signal synchronized with the clock edge included in the reception data. The transmitter/receiver is configured to switch between the first period and the second period every horizontal line in the pixel unit, and transmit and receive the transmission data and the reception data in a time division manner.

Abstract: In an imaging system, an image transmission circuit is configured to output image data to a signal line in a first mode. A signal reception circuit is configured to receive a clock control signal for adjusting a frequency of a camera clock from an image reception unit in a second mode. A signal output circuit is configured to output a first electric potential and the clock control signal to the signal line. The first electric potential corresponds to a signal level that is not included in a range of a signal level of the image data output to the signal line. A communication control circuit is configured to switch communication modes from the first mode to the second mode when the communication control circuit detects the first electric potential in the first mode.

Abstract: A semiconductor device according to an embodiment includes a plurality of element arrays, a signal-processing circuit, and a comparison-voltage generation circuit. Each element array is selectively connected to a vertical signal line and includes an amplification transistor configured to output a first analog signal on the basis of an input analog voltage and an actual value of variation of a characteristic value of each element array included in the plurality of element arrays. The comparison-voltage generation circuit is configured to output a gradually increasing or gradually decreasing comparison voltage. The signal-processing circuit includes a storage circuit and is configured to compare the first analog signal with the comparison voltage and store a timing at which the comparison voltage and a value of a second analog signal generated by adding a predetermined absolute value to the first analog signal match each other onto the storage circuit.

Abstract: In an imaging system according to an embodiment, a camera unit and an information-processing unit are connected to each other by differential-signal transmission lines. The camera unit includes a solid-state imaging device and an output driver. The solid-state imaging device is configured to operate on the basis of a power source voltage higher than a substrate voltage and generate imaging data. The output driver is configured to output a differential signal of the imaging data to the differential-signal transmission lines. The information-processing unit includes a voltage generator and a de-emphasis circuit. The voltage generator is configured to generate a reference voltage higher than the substrate voltage and lower than the power source voltage. The de-emphasis circuit is configured to control an amplitude of the differential signal by using the substrate voltage and the reference voltage.

Abstract: An image sensor includes: a pixel unit including pixels configured to generate a first signal corresponding to an amount of received light, and output the first signal; an AD converter configured to convert the first signal into a digital second signal by performing AD conversion processing for the first signal, and output the second signal; a transmitter/receiver configured to transmit and receive, in a time division manner, transmission data including at least the second signal in a first period, and reception data input from an outside in a second period; and a first generator configured to generate a first clock signal synchronized with the clock edge included in the reception data. The transmitter/receiver is configured to switch between the first period and the second period every horizontal line in the pixel unit, and transmit and receive the transmission data and the reception data in a time division manner.

Abstract: In an imaging system according to an embodiment of the present invention, a camera unit is configured to transmit imaging data to an information-processing unit as a downlink packet. The camera unit is configured to hold predetermined data in the imaging data as a transmission key. The information-processing unit is configured to receive the downlink packet, recognize the predetermined data in the imaging data as the transmission key, and generate a reception key on the basis of the transmission key. The information-processing unit is configured to transmit an uplink packet including the reception key and a register-setting signal indicating an imaging condition to the camera unit. The camera unit is configured to write the register-setting signal received with the reception key in a register when the transmission key and the reception key meet a predetermined condition.

Abstract: In an imaging system according to an embodiment of the present invention, a camera unit is configured to transmit imaging data to an information-processing unit as a downlink packet. The camera unit is configured to hold predetermined data in the imaging data as a transmission key. The information-processing unit is configured to receive the downlink packet, recognize the predetermined data in the imaging data as the transmission key, and generate a reception key on the basis of the transmission key. The information-processing unit is configured to transmit an uplink packet including the reception key and a register-setting signal indicating an imaging condition to the camera unit. The camera unit is configured to write the register-setting signal received with the reception key in a register when the transmission key and the reception key meet a predetermined condition.

Abstract: In an imaging system according to an embodiment, a camera unit and an information-processing unit are connected to each other by differential-signal transmission lines. The camera unit includes a solid-state imaging device and an output driver. The solid-state imaging device is configured to operate on the basis of a power source voltage higher than a substrate voltage and generate imaging data. The output driver is configured to output a differential signal of the imaging data to the differential-signal transmission lines. The information-processing unit includes a voltage generator and a de-emphasis circuit. The voltage generator is configured to generate a reference voltage higher than the substrate voltage and lower than the power source voltage. The de-emphasis circuit is configured to control an amplitude of the differential signal by using the substrate voltage and the reference voltage.

Abstract: A semiconductor device according to an embodiment includes a plurality of element arrays, a signal-processing circuit, and a comparison-voltage generation circuit. Each element array is selectively connected to a vertical signal line and includes an amplification transistor configured to output a first analog signal on the basis of an input analog voltage and an actual value of variation of a characteristic value of each element array included in the plurality of element arrays. The comparison-voltage generation circuit is configured to output a gradually increasing or gradually decreasing comparison voltage. The signal processing circuit includes a storage circuit and is configured to compare the first analog signal with the comparison voltage and store a timing at which the comparison voltage and a value of a second analog signal generated by adding a predetermined absolute value to the first analog signal match each other onto the storage circuit.

Abstract: In an imaging system, an image transmission circuit is configured to output image data to a signal line in a first mode. A signal reception circuit is configured to receive a clock control signal for adjusting a frequency of a camera clock from an image reception unit in a second mode. A signal output circuit is configured to output a first electric potential and the clock control signal to the signal line. The first electric potential corresponds to a signal level that is not included in a range of a signal level of the image data output to the signal line. A communication control circuit is configured to switch communication modes from the first mode to the second mode when the communication control circuit detects the first electric potential in the first mode.

Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.

Abstract: An imaging element includes: a plurality of pixels where each pixel is configured to generate an imaging signal; a noise eliminating circuit configured to eliminate a noise component included in the imaging signal; a plurality of column source follower buffers where each column source follower buffer is configured to amplify the imaging signal from which the noise component has been eliminated by the noise eliminating circuit, and output the amplified signal; a horizontal scanning circuit configured to sequentially select the column source follower buffer and output the imaging signal; and a buffer circuit which is connected with the column source follower buffer sequentially selected by the horizontal scanning circuit to form a voltage follower circuit, the buffer circuit being configured to perform impedance conversion on a voltage of the imaging signal output from the column source follower buffer, and output the converted signal to an outside.

Abstract: A noise removing circuit includes a capacitor, a buffer circuit, and a switch. The capacitor includes a first terminal and a second terminal. The buffer circuit includes a third terminal and a fourth terminal. The switch sets the capacitor and the buffer circuit to be in one of a first state and a second state. In the first state, the first terminal is connected to the fourth terminal, a reference voltage is input to the second terminal, and the third terminal is connected to the signal source. In the second state, the first terminal is connected to the signal source, and the second terminal is connected to the third terminal.

Abstract: An AD converter includes a first DAC circuit, a second DAC circuit, a comparison circuit, a control circuit, and a control switch. The comparison circuit is connected to a first output node of the first DAC circuit and a second output node of the second DAC circuit and compares an electric potential of the first output node with an electric potential of the second output node. The control circuit controls the first DAC circuit and the second DAC circuit in accordance with a result of the comparison acquired by the comparison circuit. The control switch controls turning on and off of connection between a first input node of the first DAC circuit and a second input node of the second DAC circuit.

Abstract: A signal processing system includes: a transmission channel; a common-mode signal transmitting circuit configured to output an uplink signal to the transmission channel in a common mode; a common-mode signal detecting circuit configured to detect a common-mode signal from the uplink signal transmitted by the transmission channel; a downlink reference clock signal generating circuit configured to generate a downlink reference clock signal at a second frequency with reference to the first clock edge of the common-mode signal detected by the common-mode signal detecting circuit; a downlink data generating circuit configured to generate downlink data; a differential signal transmitting circuit configured to output, as a downlink signal, the downlink data generated by the downlink data generating circuit to the transmission channel in a differential mode; and a differential signal receiving circuit configured to extract a differential signal from the downlink signal.

Abstract: In an AD converter, a first DAC circuit performs a first operation in parallel with a second operation performed by a second DAC circuit, and the first DAC circuit performs the second operation in parallel with the first operation performed by the second DAC circuit. In the first operation, electric charge corresponding to an input signal of the first DAC circuit or an input signal of the second DAC circuit is sampled. In the second operation, an AD conversion is sequentially performed on the basis of the electric charge sampled in the first operation. The first DAC circuit and the second DAC circuit alternately perform the first operation and the second operation.

Abstract: A disclosed analog-to-digital converter includes; a sampling circuit to sample a pair of analog signals as a differential input signal; a binary capacitance holding the sampled pair of analog signals and reflecting a level of a reference signal to the analog signals through the binary capacitance to generate a pair of voltage signals; a comparator including a transistor to which the voltage signals are input, to compare one of the voltage signals with the other; a correction circuit provided previously to the comparator, to output to the comparator the pair of voltage signals in which voltage dependency of stray capacitance in the input transistor is cancelled; and a controller that successively determines a value of each bit of a digital signal corresponding to the binary capacitance based on a comparison by the comparison circuit, and reflects the value of each bit of the digital signal to the reference signal.

Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.