Abstract: A first transistor is turned on during operation of a circuit block, to connect a substrate of the transistor to a first substrate voltage line. A second transistor is turned on during non-operation of the circuit block, to connect the substrate of the transistor to a second substrate voltage line. ON resistance of the second transistor is higher than that of the first transistor. A source-to-substrate voltage of the transistor being not in operation is set to be higher than that of the transistor being in operation. When a semiconductor integrated circuit switches from the operation state to the non-operation state, its substrate voltage changes gradually to a second substrate voltage. Charging/discharging currents of the substrate voltage can be dispersed so that it is possible to suppress current consumption in shifting from the operation state to the non-operation state and reduce a standby current in the non-operation state.

Abstract: A first transistor is turned on during operation of a circuit block, to connect a substrate of the transistor to a first substrate voltage line. A second transistor is turned on during non-operation of the circuit block, to connect the substrate of the transistor to a second substrate voltage line. ON resistance of the second transistor is higher than that of the first transistor. A source-to-substrate voltage of the transistor being not in operation is set to be higher than that of the transistor being in operation. When a semiconductor integrated circuit switches from the operation state to the non-operation state, its substrate voltage changes gradually to a second substrate voltage. Charging/discharging currents of the substrate voltage can be dispersed so that it is possible to suppress current consumption in shifting from the operation state to the non-operation state and reduce a standby current in the non-operation state.

Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

Abstract: In the semiconductor memory, a refresh signal is generated and the refresh operation is performed based on the refresh signal. Parity is generated when data is written and the generated parity is stored. When the refresh operation and a usual data read or write operation overlap, data in a memory cell which cannot be read because the refresh operation is given priority is determined based on the parity. Data which cannot be written because the refresh operation is given priority is held temporarily in a write data buffer. When the refresh operation is not overlapped for the usual data read or write operation, the data held in the write data buffer is rewritten in a corresponding memory cell.

Abstract: A semiconductor memory selects desired one of word lines, which belong to banks each including a memory cell array, on the basis of a main WD select signal (mwd) and sub-WD select signals (swdx and swdz) determined in accordance with an address. The main WD select signal is a pulse signal. A latch circuit latches, for a predetermined time, the state of the sub-WD select signals having changed on the basis of state changes of the main WD select signal. This allows the banks to share the main WD select signal. Since a main WD signal generator is thus shared by the banks, the area of a chip can be reduced.

Abstract: In the semiconductor memory, a refresh signal is generated and the refresh operation is performed based on there fresh signal. Parity is generated when data is written and the generated parity is stored. When the refresh operation and a usual data read or write operation are overlapped on each other, data in a memory cell which cannot be read because the refresh operation is given priority is determined based on the parity. Data which cannot be written because the refresh operation is given priority is held temporarily in a write data buffer. When the refresh operation is not overlapped on the usual data read or write operation, the data held in the write data buffer is rewritten in a corresponding memory cell.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: A semiconductor memory selects desired one of word lines, which belong to banks each including a memory cell array, on the basis of a main WD select signal (mwd) and sub-WD select signals (swdx and swdz) determined in accordance with an address. The main WD select signal is a pulse signal. A latch circuit latches, for a predetermined time, the state of the sub-WD select signals having changed on the basis of state changes of the main WD select signal. This allows the banks to share the main WD select signal. Since a main WD signal generator is thus shared by the banks, the area of a chip can be reduced.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: The semiconductor device comprises a semiconductor substrate 14 of a first conduction type; a buried semiconductor layer 38b of a second conduction type formed in a first region of the semiconductor substrate 14, spaced from a surface of the semiconductor substrate 14; a semiconductor region 38a of a second conduction type formed in a peripheral portion of a region between the surface of the semiconductor substrate 14 in the first region of the semiconductor substrate 14 and the buried semiconductor layer 38b, and connected to the buried semiconductor layer 38b; and a semiconductor region 14a of the first conduction type formed in the semiconductor substrate 14 surrounded by the buried semiconductor layer 38b and the second conduction type semiconductor region 38a. The parasitic capacitance between the source/drain diffused layer of the input/output transistor and the semiconductor substrate can be small, whereby the semiconductor device can have high operational speed.

Abstract: A power supply line is formed over a memory cell array which has arranged a plurality of memory cells using a metal wiring layer M1 which is disposed on the side closest to the memory cell array, of all the metal wiring layers. The power supply lines are formed over the memory cell array using not only an upper metal wiring layer M2 but the metal wiring layer M1 so that the wiring resistance of the power supply lines may decrease and a sufficient amount of current can be supplied to the power supply lines. Consequently, the circuits supplied with an electric current through the power supply lines become capable of high-speed operation. This is particularly effective for the high-speed operation of the circuits arranged around the memory cell array. The power supply line formed using the lower metal wiring layer M1 is connected over the memory cell array to a power supply line which is formed using the metal wiring layer M2 on the upper layer than the metal wiring layer M1.

Abstract: Connections of global data buses GDB0 and GDB1 to local data buses LDB00 to LDB04 in a bank 1 are reverse to those in a bank 0. That is, the global data bus GDB0 is connected to every other local data bus LDB00, LDB02 and LDB04 including both sides in the bank 0, and to every other local data buses LDB11 and LDB13 excluding both sides in the bank 1, while the global data bus GDB1 is connected to every other local data buses LDB01 and LDB03 excluding both sides in the bank 0, and to every other local data bus LDB10, LDB12 and LDB14 including both sides.

Abstract: To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG−Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed.

Abstract: According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.

Abstract: A transistor of a driver in the semiconductor integrated circuit according to the present invention has its gate connected to a controlling circuit, and has its drain connected to a sense amplifier. The controlling circuit supplies the gate of the transistor with a gate-to-source voltage exceeding or below other power supply voltages. The drain-to-source resistance of the transistor in the on state becomes sufficiently lower as compared with that in the case of supplying the power supply voltages between the gate and source of the transistor. Accordingly, the amplifying speed of the sense amplifier is heightened without altering the sense amplifier and the driver. Besides, the amplifying speed of the sense amplifier is heightened without raising the power supply voltage which supplies the carriers to the driver.

Abstract: A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.

Abstract: A semiconductor integrated circuit producing a given output voltage includes first and second operational amplifiers, and first and second transistors. The first and second operational amplifiers detect a voltage difference between a voltage applied to an input terminal and at least one reference voltage. The first and second transistors are turned ON or turned OFF according to the levels of voltages output from the first and second operational amplifiers. The first operational amplifier receives the output voltage at the input terminal. When the level of the output voltage becomes lower than the reference voltage, the first operational amplifier allows the first transistor to operate so as to raise the output voltage. In contrast, the second operational amplifier receives the output voltage at the input terminal. When the level of the output voltage exceeds the reference voltage, the second operational amplifier allows the second transistor to operate so as to lower the output voltage.

Abstract: On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of-an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

Abstract: In a semiconductor memory, sub-decoders in two adjacent sub-decoder groups are mirror-arranged with respect to the boundary between the two blocks. Sub-select lines are cross-connected to the sub-decoders in one sub-decoder group. This permits all sub-select lines connected to the two adjacent sub-decoder groups to be sequentially selected in a certain direction in accordance with a sequentially incremented address. Even when shift redundancy processing is performed, the order of selection of these sub-select lines does not reverse itself owing to the mirror arrangement.

Abstract: A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.