Abstract: A direct-sense activation circuit 20 is provided for a sense circuit row 12A. When a memory block 0 is activated, the direct-sense activation circuit 20 activates a direct-sense driving line in response to an activated read signal from the control circuit 18. The direct sense circuit is provided with a direct sense gate which is controlled by the voltage of a bit line and a column gate connected to the direct sense gate in series between the direct-sense driving line and a read-data bus line. A plurality of memory blocks are disposed in the direction perpendicular to the sense circuit row 12A, a column decoder 13 and a sense buffer circuit 15 are disposed so that these memory blocks are placed therebetween, and the word decoders are disposed on a side of the respective memory blocks.

Abstract: A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks.

Abstract: To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG-Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed.

Abstract: The present invention relates to a memory device including memory cells each formed of a cell transistor connected to bit and word line and a cell capacitor. The memory device includes a pre-charging circuit for pre-charging bit line to a first voltage, a sense amplifier for detecting voltages of bit lines and driving the bit lines to a second voltage for H level or a third voltage for L level, and a word line driving circuit for driving word lines to make the writing voltage for H level of the cell capacitor to a fourth voltage lower than the second voltage. The present invention is characterized in that the first voltage is lower than an intermediate value between the second and third voltages. According to the present invention, it becomes possible to prevent the voltage V.sub.

Abstract: On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

Abstract: A semiconductor memory device includes a memory cell connected to a bit line and a word line, a bit line precharge circuit which precharges the bit line to a ground voltage, and a word decoder which sets the word line to a negative voltage when the word line is not selected.

Abstract: This invention is a memory device with a structure that has eliminated the logic circuit using I/O mask signal DQM from within the critical path from the clock CLK to the predecoder and column decoder for generating column selection signal CL. The logic circuit using I/O mask signal DQM within the critical path for generating column selection signals is eliminated, and the time from when the clock is supplied until the column selection signal is generated is made as short as possible. On the other hand, to make an I/O mask possible during burst write mode, drive control of the write amplifier is performed based on I/O mask signal DQM. Specifically, activation of the write amplifier is prohibited or allowed in response to the I/O mask signal DQM.

Abstract: According to the present invention, the main word lines arranged in a row direction have a linear pattern shape, and in the region where sub word decoder circuits are formed, the pattern of the main word lines has a shape whereby the pattern branches and splits into a plurality of lines and then reconverges, in the direction of the row. In the region where the line splits, relatively small island-shaped patterns of the conducting layer are located, forming nodes which have a difference electric potential from the main word lines. The main word lines are constituted by a first metal conducting layer, similarly to the prior art. In other words, small island-shaped metal layer patterns, which are electrically different from the main word lines are formed inside the conducting metal layer pattern constituting the main word lines, similarly to island formed in the middle of a river, for example.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: A semiconductor memory device uses a wave pipeline system which can reduce a power consumption by reducing a current for charging a data bus between a memory core part and an output circuit. A single line data bus transmits read data output from the memory core part. A data bus drive circuit outputs the read read data to send to the single data bus. Each of a plurality of data latch circuits has a data input terminal connected to the data bus. A data input control circuit inputs the read data which is serially transmitted on the data bus to the data latch circuits in parallel in response to an operation of the data bus drive circuit. A data output control circuit outputs the latched read data in an order of latching by sequentially selecting outputs of the data latch circuits.

Abstract: A semiconductor memory device includes at least one cell block including an array of memory cells, a plurality of sense amplifiers which temporarily hold data of the memory cells, a first data bus connected to the plurality of sense amplifiers via first gates, and a second data bus having a direct electrical connection to the first data bus and being laid out to extend through a position of the at least one cell block.

Abstract: An electronic device includes a first circuit which refers to an external clock and thus produces a first internal clock, and a second circuit which refers to the first internal clock and thus produces a second internal clock. The first circuit has a first phase error between the external clock and the first internal clock, and the second circuit has a second phase error between the first internal clock and the second internal clock. The first phase error has a sign reverse to that of the second phase error.

Abstract: A semiconductor integrated circuit system includes a first power line which supplies a first source power voltage, and a second power line which supplies a second source power voltage. A first edge detecting unit outputs a first edge detection signal when a rising edge of the first source power voltage is detected. A second edge detecting unit outputs a second edge detection signal when a rising edge of the second source power voltage is detected. An output unit is connected to the first power line, and outputs data to a data terminal in a data output cycle and sets the data terminal in a high-impedance state in response to the first edge detection signal. An output control unit is connected to the second power line, and controls the output unit in accordance with a read-data signal in the data output cycle, and controls the output unit in response to the second edge detection signal, so that the data terminal is set in the high-impedance state by the output unit.

Abstract: A semiconductor includes a Lead-on-chip (LOC) structure. A bonding pad solely for receiving a signal is formed parallel to a perimeter on top in the middle of the element-formation surface. A bonding pad solely for transmitting a signal is formed around the periphery of the element-formation surface, and an inner lead solely for receiving a signal has its tip positioned parallel to the perimeter on top in the middle of the element-formation surface. An inner lead solely for transmitting a signal has its tip positioned on top of the periphery of the element-formation surface.