Patents by Inventor Masatoshi Hase

Masatoshi Hase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250022873
    Abstract: A bonding layer including a first metal region is disposed on at least a portion of an upper surface of a support substrate. An underlying layer including a sub-collector region that is made of a conductive semiconductor material and is electrically connected to the first metal region is disposed on the bonding layer. A first transistor including a collector layer electrically connected to the sub-collector region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer is disposed on the sub-collector region. On the sub-collector region, a collector electrode electrically connected to the sub-collector region is located outward of the first transistor to overlap the first metal region in plan view.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masayuki AOIKE, Shinnosuke TAKAHASHI, Masatoshi HASE, Fumio HARIMA
  • Publication number: 20240396516
    Abstract: A balanced-to-unbalanced transformer circuit is formed with a transmission line including a main line and a sub-line which are coupled to each other. The main line comprises at least one wiring line. The sub-line comprises multiple wiring lines which are connected in parallel to one another and which are other than the at least one wiring line. Each of the wiring lines of the sub-line is coupled to the at least one wiring line of the main line.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Seiko NETSU, Masatoshi HASE
  • Publication number: 20240388264
    Abstract: A Class E amplifier is configured to amplify a differential signal. Two output nodes of the Class E amplifier are connected to the power supply terminal with at least one choke inductor interposed therebetween. The Class E amplifier includes two transistors. The two transistors each includes a base or a gate connected to a corresponding one of two input nodes of the Class E amplifier and a collector or a drain connected to a corresponding one of the two output nodes of the Class E amplifier. First capacitors are each connected between the collector or the drain and an emitter or a source of a corresponding one of the two transistors. A first inductor is connected between the collector or the drain of one of the two transistors and the collector or the drain of the other of the two transistors.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Masatoshi HASE, Seiko NETSU
  • Patent number: 12119852
    Abstract: A first primary line has a first node at one end and a third node at another end and transmits a radio-frequency signal between the first node and the third node. A second primary line has a second node at one end and a fourth node at another end and transmits a radio-frequency signal between the second node and the fourth node. A first secondary line has a portion connected to the second node and is electromagnetically coupled to the first primary line. The second secondary line has a portion connected to the first node and has another end connected to a portion of the first secondary line. The second secondary line is electromagnetically coupled to the second primary line. A first capacitor is connected in parallel to a portion of the second primary line or a portion of the second secondary line.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: October 15, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Seiko Netsu, Masatoshi Hase
  • Publication number: 20240333231
    Abstract: A power amplifier circuit includes a distortion compensation amplifier circuit that includes a first amplifier that amplifies a first signal distributed from an input signal, and a second amplifier connected in parallel to the first amplifier, that amplifies a second signal distributed from the input signal and having a different phase from the first signal, and outputs an amplified signal obtained by combining a signal output from the first amplifier and the second amplifier, and an output amplifier circuit that outputs an output signal obtained by amplifying the amplified signal. The distortion compensation amplifier circuit further includes a control circuit that controls, based on power of the input signal, the first gain and the second gain to compensate for a change in a phase of the output amplifier circuit with respect to a change in the power of the signal input to the output amplifier circuit.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 3, 2024
    Inventors: Masatoshi HASE, Seiko NETSU, Shingo YANAGIHARA
  • Patent number: 12009790
    Abstract: A first transmission line and a third transmission line are disposed at different positions in a thickness direction of a substrate. The third transmission line includes a first end portion connected to one end portion of the first transmission line, and a second end portion that is grounded. The first transmission line is electromagnetically coupled to the third transmission line. The first transmission line has a coil pattern and the third transmission line has a partially open loop pattern.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: June 11, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masatoshi Hase
  • Publication number: 20240162866
    Abstract: There are included a first amplifier and a second amplifier electrically connected to a stage subsequent to the first amplifier, a third amplifier and a fourth amplifier electrically connected to a stage subsequent to the third amplifier, a phase shifter that makes a phase of a radio-frequency signal passing through a first path different from a phase of a radio-frequency signal passing through a second path, a first bias circuit that supplies a bias to the first amplifier and the third amplifier, a second bias circuit that supplies a bias to the first amplifier and the second amplifier, and a third bias circuit that supplies a bias to the third amplifier and the fourth amplifier. The second amplifier includes a second transistor, the fourth amplifier includes a fourth transistor, the second bias circuit includes a sixth transistor, and the third bias circuit includes a seventh transistor.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventor: Masatoshi HASE
  • Publication number: 20240162870
    Abstract: A main line (transmission line) having a first end and a second end. A sub-line (transmission line) coupled to the main line. An unbalanced signal is input to and output from an unbalanced node connected to the first end. A balanced signal is input to and output from a first balanced node and a second balanced node. The main line and the sub-line are coupled to each other. A direction of the main line is identical to a direction of the sub-line. The second end and the third end are connected to a reference potential. The first balanced node and the second balanced node are connected to the unbalanced node and the fourth end, respectively. A first LC resonant circuit is connected between the second end and the reference potential or the third end and the reference potential.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Inventors: Masatoshi HASE, Koudai SUGIYAMA, Masamichi TOKUDA, Seiko NETSU
  • Publication number: 20240162871
    Abstract: A main line (transmission line) has a first end and a second end. A sub-line (transmission line) coupled to the main line has a third end and a fourth end. The main line and the sub-line are coupled to each other. A direction of the main line is identical to a direction of the sub-line. An unbalanced node is connected to the first end. The first balanced node is connected to the first end, and the second balanced node is connected to the fourth end. The second end and the third end are connected to a reference potential. A first LC resonant circuit is connected between the first balanced node and the unbalanced node, the second balanced node and the fourth end, or the first end and the unbalanced node.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Inventors: Masatoshi HASE, Koudai SUGIYAMA, Masamichi TOKUDA, Seiko NETSU
  • Publication number: 20240146271
    Abstract: A first transmission line transformer receives and outputs an unbalanced signal and performs impedance transformation. A second transmission line transformer performs unbalanced-to-balanced transformation. The first transmission line transformer includes a first main line and a first sub-line. The direction of the first main line is identical to the direction of the first sub-line. An end of the first sub-line is grounded. An end of the first main line is coupled to the unbalanced-signal input/output node. The second transmission line transformer includes a second main line and a second sub-line. The direction of the second main line is identical to a direction of the second sub-line. An end of the second main line and the second sub-line are grounded. An end of the second main line and the second sub-line are coupled to the balanced-signal input/output nodes.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 2, 2024
    Inventors: Masatoshi HASE, Koudai SUGIYAMA, Masamichi TOKUDA, Seiko NETSU
  • Patent number: 11955931
    Abstract: A power amplifier unit includes a power amplifier circuit that amplifies a radio-frequency input signal, a first impedance matching circuit that performs impedance matching for an output signal of the power amplifier circuit, a second-order harmonic termination circuit on an output side of the first impedance matching circuit and that reflects at least part of even-ordered and odd-ordered harmonics contained in a signal input from the first impedance matching circuit to output the at least part of the harmonics from an input terminal as a radio-frequency signal and outputs a radio-frequency signal containing a fundamental and the remainder of the harmonics from an output terminal, and a filter that is on a subsequent stage of the second-order harmonic termination circuit, that attenuates at least part of the even-ordered and odd-ordered harmonics, and that outputs a radio-frequency signal including the fundamental and the remainder of the even-ordered and odd-ordered harmonics.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: April 9, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masatoshi Hase, Mitsunori Samata
  • Publication number: 20240088850
    Abstract: A transmission circuit appropriately controls output power in response to fluctuations in the impedance of a load. A transmission circuit includes: a transistor to which a bias current IB1 is supplied and that amplifies and outputs an input signal RFin; a transistor to which a bias current IB2 is supplied, that has a collector connected to the collector of the transistor, and that amplifies and outputs the input signal; a current generation circuit that generates a current I2 on the basis of a current I1 from the emitter of the transistor; and a bias control circuit that outputs a first bias control signal for controlling the bias current IB1 and a second bias control signal for controlling the bias current IB2 on the basis of the current I2.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Masatoshi HASE, Tsutomu OONARO, Takashi SOGA
  • Patent number: 11876032
    Abstract: A bond layer including at least one metal region in a plan view is disposed on a surface layer portion of a substrate formed from a semiconductor. A semiconductor element is disposed on the bond layer and includes a first transistor disposed on a first metal region that is a metal region as the at least one metal region of the bond layer and including a collector layer electrically coupled to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. A first emitter electrode is disposed on the emitter layer of the first transistor. A first conductor protrusion is disposed on the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion is higher than that of each of the collector layer, the base layer, and the emitter layer of the first transistor.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 16, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinnosuke Takahashi, Masayuki Aoike, Masatoshi Hase, Fumio Harima
  • Patent number: 11784609
    Abstract: A power amplifier circuit includes an amplifier that receives an input signal with an alternating current and outputs an output signal obtained by amplifying power of the input signal to a first node; an inductive element that is connected between the first node and a second node; and a variable capacitor that is connected between the second node and a reference potential, and whose electrostatic capacitance increases as power of the output signal increases.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: October 10, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Masatoshi Hase, Norio Hayashi, Kazuo Watanabe, Yuuri Honda
  • Publication number: 20230299725
    Abstract: A first transmission line and a third transmission line are disposed at different positions in a thickness direction of a substrate. The third transmission line includes a first end portion connected to one end portion of the first transmission line, and a second end portion that is grounded. The first transmission line is electromagnetically coupled to the third transmission line. The first transmission line has a coil pattern and the third transmission line has a partially open loop pattern.
    Type: Application
    Filed: November 2, 2022
    Publication date: September 21, 2023
    Inventor: Masatoshi HASE
  • Patent number: 11750152
    Abstract: Provided is a power amplifier circuit that can increase output power and also reduce the effect of intermodulation distortion. The power amplifier circuit includes a power divider, a distortion compensation circuit provided on the secondary path, a power combiner, and a first amplifier configured. The distortion compensation circuit includes a generation circuit configured to generate the second-harmonic wave of the input signal, a filter circuit configured to attenuate the fundamental wave and pass the second-harmonic wave, and a phase adjustment circuit configured to adjust the phase of the second-harmonic wave.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: September 5, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masatoshi Hase
  • Patent number: 11677358
    Abstract: A power amplifier circuit includes a substrate and a semiconductor chip disposed on or above the substrate. The semiconductor chip includes a power amplifier unit that amplifies an RF signal, a ground terminal to which a ground of the power amplifier unit is coupled, and a first circuit element having a first end electrically coupled to the ground terminal without any portion outside the semiconductor chip interposed therebetween, and having a second end. The substrate includes a second circuit element having a first end electrically coupled to an output of the power amplifier unit and a second end electrically coupled to the second end of the first circuit element. The first and second circuit elements constitute a harmonic wave termination circuit. The harmonic wave termination circuit reflects, to the power amplifier unit, a harmonic wave component of the amplified RF signal output from the power amplifier unit.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: June 13, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masatoshi Hase, Satoshi Tanaka
  • Publication number: 20230155558
    Abstract: A power amplifier circuit includes amplifying transistors electrically cascade-connected, amplifying a signal supplied to a base, and outputting an amplified signal; a first resistive element having end parts connected to the base of a first amplifying transistor; a second resistive element having end parts connected to the base of a second amplifying transistor, which is an amplifying transistor located closer to an input side than the first amplifying transistor; a first bias supplying transistor having an emitter connected to one of the end parts of the first resistive element; a second bias supplying transistor having an emitter connected to one of the end parts of the second resistive element; and a bias current compensation transistor having a base connected to the end part of the first resistive element, a collector connected to the end part of the second resistive element, and an emitter connected to ground.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 18, 2023
    Inventor: Masatoshi HASE
  • Publication number: 20230053456
    Abstract: A power amplifier unit includes a power amplifier circuit that amplifies a radio-frequency input signal, a first impedance matching circuit that performs impedance matching for an output signal of the power amplifier circuit, a second-order harmonic termination circuit on an output side of the first impedance matching circuit and that reflects at least part of even-ordered and odd-ordered harmonics contained in a signal input from the first impedance matching circuit to output the at least part of the harmonics from an input terminal as a radio-frequency signal and outputs a radio-frequency signal containing a fundamental and the remainder of the harmonics from an output terminal, and a filter that is on a subsequent stage of the second-order harmonic termination circuit, that attenuates at least part of the even-ordered and odd-ordered harmonics, and that outputs a radio-frequency signal including the fundamental and the remainder of the even-ordered and odd-ordered harmonics.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 23, 2023
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masatoshi HASE, Mitsunori SAMATA
  • Patent number: 11528012
    Abstract: An active balun circuit includes first and second transistors having emitters electrically coupled to each other and configured to output differential signals and a circuit element coupled between the connection point of the emitter of the first transistor and the emitter of the second transistor and a reference potential. The impedance of the circuit element at a particular frequency of the input signal appears significantly larger than impedances at other frequencies. An input signal from an input terminal is inputted to the base of the first transistor. The reference potential is applied to the base of the second transistor. A supply voltage is applied to the collector of the first transistor and the collector of the second transistor. A signal from the collector of the first transistor and a signal from the collector of the second transistor are outputted as the differential signals.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: December 13, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Satoshi Tanaka, Kiichiro Takenaka, Masatoshi Hase