Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Abstract: A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes selecting each word line through a row decoder connected to all word lines to switch all synaptic NVRAM cells of the selected lines. The method includes driving, on the selected lines, a wave generated by a PLL circuit connected to the row decoder. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines through a column decoder connected to all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.

Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Abstract: The present invention relates to a method for producing a hexafluoromanganate(IV), said method being characterized by comprising: inserting an anode and a cathode into a reaction solution that contains a compound containing manganese having an atomic valence of less than 4 and/or manganese having an atomic valence of more than 4 and hydrogen fluoride; and then applying an electric current having an electric current density of 100 to 1000 A/m2 between the anode and the cathode. According to the present invention, it becomes possible to produce a hexafluoromanganate(IV) in which the content ratio of manganese having an atomic valence of 4 is high and the contamination with oxygen is reduced and which has high purity. When a complex fluoride red phosphor is produced using the hexafluoromanganate(IV) as a raw material, the phosphor produced has high luminescence properties, particularly high internal quantum efficiency.

Abstract: A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes selecting each word line through a row decoder connected to all word lines to switch all synaptic NVRAM cells of the selected lines. The method includes driving, on the selected lines, a wave generated by a PLL circuit connected to the row decoder. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines through a column decoder connected to all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.

Abstract: A portable electronic device has a control unit including a processor whose clock frequency is variable, a temperature sensor, a housing that encases the control unit and temperature sensor, and a touch sensor that is able to detect touching to the surface of the housing. The control unit obtains a measured value of temperature from the temperature sensor, calculates an estimated value of surface temperature of the housing using the measured value and a first heat transfer model when the touch sensor has not detected touching, calculates the estimated value using the measured value and a second heat transfer model when the touch sensor has detected touching, decreases an upper limit for the clock frequency when the estimated value is higher than or equal to a threshold, and increases the upper limit for the clock frequency when the estimated value is lower than the threshold.

Abstract: A memory cell structure includes a plurality of write lines arranged for writing a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being used for writing the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing one of a second set of states to each unit cell included in the corresponding cell component, the first and second sets each having a predetermined number of states, and the first set depending on the second set, and a read line arranged for reading the synapse state from the synapse memory cell.

Abstract: Provided is a method for producing a phosphor having a chemical composition represented by formula (I), A2MF6:Mn (I) (A is one type or more of an alkali metal selected from Li, Na, K, Rb, and Cs, and includes at least Na and/or K, and M is one type or more of a tetravalent element selected from Si, Ti, Zr, Hf, Ge, and Sn.), the method comprising preparing a first hydrofluoric acid solution containing M and a second hydrofluoric acid solution containing A as well as either dissolving a compound containing Mn in either the first hydrofluoric acid solution or the second hydrofluoric acid solution or preparing a separate solution in which the compound containing Mn is dissolved. When the solutions are mixed to precipitate the phosphor of the formula (I), the solutions are mixed so that the concentration of M is 0.1 to 0.5 mol/liter when all the solutions are mixed. According to the present invention, a complex fluoride phosphor having excellent luminescence properties can be produced stably with high yield.

Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Abstract: A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes selecting each word line through a row decoder connected to all word lines to switch all synaptic NVRAM cells of the selected lines. The method includes driving, on the selected lines, a wave generated by a PLL circuit connected to the row decoder. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines through a column decoder connected to all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.

Abstract: A processor disposed over a substrate of an electronic apparatus acquires a first measured value from a temperature sensor disposed on the substrate, and calculates surface temperature of a surface of an enclosure of the electronic apparatus on the basis of a transfer function G(s) based on a first thermal resistance and a first thermal capacitance between a heat source over the substrate and the surface of the enclosure, a transfer function H(s) based on a second thermal resistance and a second thermal capacitance between the heat source and the temperature sensor, and the first measured value.

Abstract: A neuromorphic memory system including neuromorphic memory arrays. Each neuromorphic memory array includes rows and columns of neuromorphic memory cells. A column of postsynaptic circuits is electrically coupled to postsynaptic spike timing dependent plasticity (STDP) lines. Each postsynaptic STDP line is coupled to a row of neuromorphic memory cells. A column of summing circuits is electrically coupled to postsynaptic leaky integrate and fire (LIF) lines. Each postsynaptic LIF line is coupled to the row of neuromorphic memory cells at a respective memory array. Each summing circuit provides a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit.

Abstract: A memory cell structure includes a plurality of write lines arranged for writing a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being used for writing the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing one of a second set of states to each unit cell included in the corresponding cell component, the first and second sets each having a predetermined number of states, and the first set depending on the second set, and a read line arranged for reading the synapse state from the synapse memory cell.

Abstract: A memory cell structure includes a synapse memory cell including plural cell components, each of the plural cell components including a unit cell, plural write lines arranged for writing a synapse state to the synapse memory cell, each of the plural write lines being used for writing one of a first set of a predetermined number of states to a corresponding cell component by writing one of a second set of the predetermined number of states to the unit cell included in the corresponding cell component, the first set depending on the second set and a number of the unit cell included in the corresponding cell component, and a read line arranged for reading the synapse state from the synapse memory cell, the read line being used for reading one of the first set of the predetermined number of states from all of the plural cell components simultaneously.

Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Abstract: A wavelength conversion member which is a resin-molded article made of at least one type of thermoplastic resin selected from polyolefins, polystyrene, styrene copolymers, fluorocarbon resins, acrylic resins, nylons, polyester resins, polycarbonate resins, vinyl chloride resins, and polyether resins. The thermoplastic resin contains less than or equal to 30 mass % of a complex fluoride fluorophore represented by A2(M1-xMnx)F6 (M is at least one type of tetravalent element selected from Si, Ti, Zr, Hf, Ge, and Sn; A is at least one type of alkali metal selected from Li, Na, K, Rb, and Cs and including at least Na and/or K; and x is from 0.001 to 0.3) and having a particle diameter D50, which is the median diameter at a cumulative volume of 50% in particle size distribution, of from 2 ?m to 200 ?m inclusive. The complex fluoride fluorophore being dispersed in the thermoplasticresin.

Abstract: An electronic apparatus includes a housing, a substrate in the housing, components on the substrate, a reference temperature sensor, temperature sensors for the respective components, and an arithmetic processing unit. The arithmetic processing unit estimates an outside air temperature by using a reference temperature, temperatures acquired by the temperature sensors, first transfer functions, second transfer functions, and third transfer functions, and estimates a surface temperature of the housing based on the outside air temperature. Each first transfer function is defined based on a thermal resistance and a thermal time constant from a component to the reference temperature sensor. Each second transfer function is defined based on a thermal resistance and a thermal time constant from a component to an individual temperature sensor. Each third transfer function is defined based on a thermal resistance and a thermal time constant from a component to a surface of the housing.

Abstract: A memory cell structure includes a synapse memory cell including plural cell components, each of the plural cell components including a unit cell, plural write lines arranged for writing a synapse state to the synapse memory cell, each of the plural write lines being used for writing one of a first set of a predetermined number of states to a corresponding cell component by writing one of a second set of the predetermined number of states to the unit cell included in the corresponding cell component, the first set depending on the second set and a number of the unit cell included in the corresponding cell component, and a read line arranged for reading the synapse state from the synapse memory cell, the read line being used for reading one of the first set of the predetermined number of states from all of the plural cell components simultaneously.

Abstract: A tunable resistance device and methods of forming the same include a magnetic fixed layer having a fixed magnetization, a magnetic free layer, and a non-magnetic conductive layer directly between the magnetic fixed layer and the magnetic free layer. The magnetic fixed layer, the magnetic free layer, and the non-magnetic conductive layer are formed in a lattice of wires, with each wire in the lattice being formed from a stack of the magnetic fixed layer, the magnetic free layer, and the non-magnetic conductive layer.