Patents by Inventor Masatoshi Kunieda
Masatoshi Kunieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12089330Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on surface of the insulating layer and including a conductor pad, a covering layer covering a portion of the insulating layer, an optical waveguide positioned on the surface of the insulating layer and including core part, and a conductor post including plating metal and formed on the conductor pad such that the post is penetrating through the covering layer and connected to a component. The insulating layer has component region covered by the component when the component is connected, the core part has side surface extending in direction along the surface of the insulating layer, the side surface has an exposed portion exposed in the component region and facing the opposite direction with respect to the insulating layer, and distance between the exposed portion and the surface of the insulating layer is greater than thickness of the covering layer.Type: GrantFiled: June 28, 2022Date of Patent: September 10, 2024Assignee: IBIDEN CO., LTD.Inventor: Masatoshi Kunieda
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Publication number: 20240272355Abstract: A wiring substrate includes an electrical wiring part including insulating layers and conductor layers, and an optical wiring part formed on a surface of the electrical wiring part and including a support plate and an optical waveguide formed on the support plate. The optical wiring part is formed such that the optical waveguide includes at least one core part that transmits light and a cladding part surrounding the at least one core part and that the support plate has a thermal expansion coefficient that is lower than a thermal expansion coefficient of the optical waveguide.Type: ApplicationFiled: April 19, 2024Publication date: August 15, 2024Applicant: IBIDEN CO., LTD.Inventor: Masatoshi KUNIEDA
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Publication number: 20240255695Abstract: A wiring substrate includes an insulating layer, a conductor pad that is formed on a surface of the insulating layer and is connected to a component such that the insulating layer has a component region that is covered by the component connected to the conductor pad, and an optical waveguide including a core part that transmits light and is positioned on an outer side of the component region of the insulating layer such that the core part has an end surface exposed and facing a component region side. The optical waveguide is positioned such that the end surface of the core part is adjacent to the component region.Type: ApplicationFiled: April 11, 2024Publication date: August 1, 2024Applicant: IBIDEN CO., LTD.Inventor: Masatoshi KUNIEDA
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Publication number: 20230007771Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on surface of the insulating layer and including a conductor pad, a covering layer covering a portion of the insulating layer, an optical waveguide positioned on the surface of the insulating layer and including core part, and a conductor post including plating metal and formed on the conductor pad such that the post is penetrating through the covering layer and connected to a component. The insulating layer has component region covered by the component when the component is connected, the core part has side surface extending in direction along the surface of the insulating layer, the side surface has an exposed portion exposed in the component region and facing the opposite direction with respect to the insulating layer, and distance between the exposed portion and the surface of the insulating layer is greater than thickness of the covering layer.Type: ApplicationFiled: June 28, 2022Publication date: January 5, 2023Applicant: IBIDEN CO., LTD.Inventor: Masatoshi KUNIEDA
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Publication number: 20230007768Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on a surface of the insulating layer and including a conductor pad, a covering layer formed on the insulating layer and covering a portion of the insulating layer, an optical waveguide positioned on the surface of the insulating layer and including a core part, and a conductor post including plating metal and formed on the conductor pad such that the conductor post is penetrating through the covering layer and connected to a component. The insulating layer has a component region covered by the component when the component is connected to the conductor post, the core part has an end surface facing the opposite direction with respect to the insulating layer and exposed in the component region and a distance between the end surface and the surface of the insulating layer is greater than a thickness of the covering layer.Type: ApplicationFiled: June 28, 2022Publication date: January 5, 2023Applicant: IBIDEN CO., LTD.Inventor: Masatoshi KUNIEDA
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Patent number: 11071945Abstract: A filter membrane includes a membrane having through holes that selectively separates specific material in processing medium, the membrane including first, second and third layers such that the first layer has first surface that is supplied with processing medium, the third layer has second surface on the opposite side of the first surface, and the second layer is formed between the first and third layers. The first layer includes first convex and concave portions, the third layer includes second convex and concave portions each having a larger area than each first concave portion, the second convex portions are formed to surround the second concave portions and connected to one another, the second layer has through holes connecting the second concave portions and first set of the first concave portions, and the first concave portions include second set in regions opposing the second convex portions that is connected to each other.Type: GrantFiled: January 29, 2019Date of Patent: July 27, 2021Assignee: IBIDEN CO., LTD.Inventors: Masatoshi Kunieda, Hirokazu Higashi, Tatsuhiro Kawai
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Publication number: 20190232218Abstract: A filter membrane includes a membrane having through holes that selectively separates specific material in processing medium, the membrane including first, second and third layers such that the first layer has first surface that is supplied with processing medium, the third layer has second surface on the opposite side of the first surface, and the second layer is formed between the first and third layers. The first layer includes first convex and concave portions, the third layer includes second convex and concave portions each having a larger area than each first concave portion, the second convex portions are formed to surround the second concave portions and connected to one another, the second layer has through holes connecting the second concave portions and first set of the first concave portions, and the first concave portions include second set in regions opposing the second convex portions that is connected to each other.Type: ApplicationFiled: January 29, 2019Publication date: August 1, 2019Applicant: IBIDEN CO., LTD.Inventors: Masatoshi KUNIEDA, Hirokazu HIGASHI, Tatsuhiro KAWAI
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Publication number: 20180154317Abstract: A filter membrane for selectively separating a specific material from other materials in a processing medium includes a membrane including resin material and having openings formed such that the openings selectively separate a specific material from other materials in a processing medium. The membrane has a first surface and a second surface on the opposite side with respect to the first surface such that the first surface receives the processing medium supplied to the membrane, the openings are formed through the membrane such that each of the openings has an opening part extending from the second surface toward the first surface and an expansion part expanding a size of the opening part and extending from the opening part to the first surface, and the first surface of the membrane is divided into multiple regions.Type: ApplicationFiled: December 5, 2017Publication date: June 7, 2018Applicant: IBIDEN CO., LTD.Inventors: Masatoshi Kunieda, Hirokazu Higashi
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Patent number: 9986642Abstract: A method for manufacturing a printed wiring board includes forming, on a surface of an insulating layer, a patterned catalyst film including a catalyst for electroless plating such that the patterned catalyst film has a pattern corresponding to a conductor circuit, and applying electroless plating on the patterned catalyst film such that a conductor metal is deposited on the patterned catalyst film and that the conductor circuit is formed on the surface of the insulating layer.Type: GrantFiled: July 22, 2016Date of Patent: May 29, 2018Assignee: IBIDEN CO., LTD.Inventors: Masatoshi Kunieda, Takafumi Okumura
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Patent number: 9935029Abstract: A printed wiring board for package-on-package includes a first insulating layer, a wiring layer including a conductor pattern and formed on first surface of the first insulating layer, a second insulating layer formed on first surface side of the first insulating layer, electrodes formed in through holes of the first insulating layer respectively such that the electrodes electrically connect to the conductor pattern and have exposed surfaces exposed from second surface of the first insulating layer, first pads formed on the second insulating layer and positioned to connect an IC chip in center portion of the second insulating layer, second pads formed on the second insulating layer and positioned in outer edge portion of the second insulating layer to connect a second printed wiring board, and via conductors formed in the second insulating layer such that the via conductors electrically connect the first and second pads to the conductor pattern.Type: GrantFiled: February 29, 2016Date of Patent: April 3, 2018Assignee: IBIDEN CO., LTD.Inventors: Takashi Kariya, Shigeru Yamada, Masatoshi Kunieda
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Patent number: 9706663Abstract: A printed wiring board includes a first resin insulating layer, a first conductor pattern including first mounting pads formed on the first resin insulating layer, and a wiring structure positioned on the first resin insulating layer and including a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes second mounting pads. The second mounting pads are embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane.Type: GrantFiled: August 31, 2015Date of Patent: July 11, 2017Assignee: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Masatoshi Kunieda, Makoto Terui, Takashi Kariya
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Patent number: 9613893Abstract: A wiring substrate includes a first outermost conductor layer, a first outermost insulating layer covering the first conductor layer, a second outermost conductor layer formed on opposite side of the first conductor layer, and a second outermost insulating layer covering the second conductor layer. The first insulating layer has first openings such that the first openings are exposing first conductor pads including portions of the first conductor layer, the second insulating layer has second openings such that the second openings are exposing second conductor pads including portions of the second conductor layer, each of the first conductor pads has a first plating layer recessed with respect to outer surface of the first insulating layer, and each of the second conductor pads has a second plating layer formed flush with outer surface of the second insulating layer or having bump shape protruding from the outer surface of the second insulating layer.Type: GrantFiled: July 15, 2015Date of Patent: April 4, 2017Assignee: IBIDEN CO., LTD.Inventors: Makoto Terui, Ryojiro Tominaga, Masatoshi Kunieda, Noriki Sawada
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Patent number: 9565756Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer, a second insulation layer formed on the first insulation layer and the first conductive patterns and having an opening portion, a wiring structure accommodated in the opening portion of the second insulation layer and including an insulation layer and conductive patterns on the insulation layer, second conductive patterns formed on the second insulation layer; and a via conductor formed in the second insulation layer and connecting one of the first conductive patterns and one of the second conductive patterns.Type: GrantFiled: March 29, 2013Date of Patent: February 7, 2017Assignee: IBIDEN CO., LTD.Inventors: Makoto Terui, Daiki Komatsu, Masatoshi Kunieda
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Publication number: 20170027057Abstract: A method for manufacturing a printed wiring board includes forming, on a surface of an insulating layer, a patterned catalyst film including a catalyst for electroless plating such that the patterned catalyst film has a pattern corresponding to a conductor circuit, and applying electroless plating on the patterned catalyst film such that a conductor metal is deposited on the patterned catalyst film and that the conductor circuit is formed on the surface of the insulating layer.Type: ApplicationFiled: July 22, 2016Publication date: January 26, 2017Applicant: IBIDEN CO., LTD.Inventors: Masatoshi KUNIEDA, Takafumi OKUMURA
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Patent number: 9532468Abstract: A wiring board includes a first resin insulating layer, conductor pads on the first insulating layer including first and second conductor pads, a second resin insulating layer on the first insulating layer covering the first and second pads, an outermost conductor layer on the second insulating layer including first and second outermost wiring layers, via conductors through the second insulating layer including a first via conductor connecting the first wiring layer and first pad and a second via conductor connecting the second wiring layer and second pad, and a solder resist layer on the second insulating layer such that the solder resist layer is covering the first wiring layer and has one or more openings exposing the second wiring layer. The first wiring layer includes first main metal, and the second wiring layer includes second main metal which is different from the first metal of the first wiring layer.Type: GrantFiled: November 21, 2014Date of Patent: December 27, 2016Assignee: IBIDEN CO., LTD.Inventors: Masatoshi Kunieda, Makoto Terui, Ryoujiro Tominaga, Takashi Kariya
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Publication number: 20160268188Abstract: A printed wiring board for package-on-package includes a first insulating layer, a wiring layer including a conductor pattern and formed on first surface of the first insulating layer, a second insulating layer formed on first surface side of the first insulating layer, electrodes formed in through holes of the first insulating layer respectively such that the electrodes electrically connect to the conductor pattern and have exposed surfaces exposed from second surface of the first insulating layer, first pads formed on the second insulating layer and positioned to connect an IC chip in center portion of the second insulating layer, second pads formed on the second insulating layer and positioned in outer edge portion of the second insulating layer to connect a second printed wiring board, and via conductors formed in the second insulating layer such that the via conductors electrically connect the first and second pads to the conductor pattern.Type: ApplicationFiled: February 29, 2016Publication date: September 15, 2016Applicant: IBIDEN CO., LTD.Inventors: Takashi KARIYA, Shigeru YAMADA, Masatoshi KUNIEDA
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Patent number: 9431347Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and having a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and form a distance between adjacent first and third mounting pads which is greater than a distance between adjacent first mounting pads.Type: GrantFiled: June 3, 2014Date of Patent: August 30, 2016Assignee: IBIDEN CO., LTD.Inventors: Masatoshi Kunieda, Makoto Terui, Asuka Il, Yoshinori Shizuno
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Patent number: 9433085Abstract: An electronic component includes an insulation layer, an alignment mark positioned on a first surface of the insulation layer, and an adhesive layer including an optically opaque agent and formed on the first surface of the insulation layer or a second surface of the insulation layer on the opposite side with respect to the first surface of the insulation layer. The adhesive layer has an opening portion formed at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.Type: GrantFiled: April 23, 2014Date of Patent: August 30, 2016Assignee: IBIDEN CO., LTD.Inventors: Yoshinori Shizuno, Makoto Terui, Masatoshi Kunieda, Asuka Ii
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Patent number: 9425159Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and including a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and are set off from the second mounting pads toward the semiconductor element.Type: GrantFiled: June 3, 2014Date of Patent: August 23, 2016Assignee: IBIDEN CO., LTD.Inventors: Makoto Terui, Masatoshi Kunieda, Yoshinori Shizuno, Asuka Il
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Patent number: 9338886Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.Type: GrantFiled: June 4, 2014Date of Patent: May 10, 2016Assignee: IBIDEN CO., LTD.Inventors: Toshiki Furutani, Daiki Komatsu, Masatoshi Kunieda, Naomi Fujita, Nobuya Takahashi