Patents by Inventor Masatoshi Kunieda

Masatoshi Kunieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230007768
    Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on a surface of the insulating layer and including a conductor pad, a covering layer formed on the insulating layer and covering a portion of the insulating layer, an optical waveguide positioned on the surface of the insulating layer and including a core part, and a conductor post including plating metal and formed on the conductor pad such that the conductor post is penetrating through the covering layer and connected to a component. The insulating layer has a component region covered by the component when the component is connected to the conductor post, the core part has an end surface facing the opposite direction with respect to the insulating layer and exposed in the component region and a distance between the end surface and the surface of the insulating layer is greater than a thickness of the covering layer.
    Type: Application
    Filed: June 28, 2022
    Publication date: January 5, 2023
    Applicant: IBIDEN CO., LTD.
    Inventor: Masatoshi KUNIEDA
  • Publication number: 20230007771
    Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on surface of the insulating layer and including a conductor pad, a covering layer covering a portion of the insulating layer, an optical waveguide positioned on the surface of the insulating layer and including core part, and a conductor post including plating metal and formed on the conductor pad such that the post is penetrating through the covering layer and connected to a component. The insulating layer has component region covered by the component when the component is connected, the core part has side surface extending in direction along the surface of the insulating layer, the side surface has an exposed portion exposed in the component region and facing the opposite direction with respect to the insulating layer, and distance between the exposed portion and the surface of the insulating layer is greater than thickness of the covering layer.
    Type: Application
    Filed: June 28, 2022
    Publication date: January 5, 2023
    Applicant: IBIDEN CO., LTD.
    Inventor: Masatoshi KUNIEDA
  • Patent number: 11071945
    Abstract: A filter membrane includes a membrane having through holes that selectively separates specific material in processing medium, the membrane including first, second and third layers such that the first layer has first surface that is supplied with processing medium, the third layer has second surface on the opposite side of the first surface, and the second layer is formed between the first and third layers. The first layer includes first convex and concave portions, the third layer includes second convex and concave portions each having a larger area than each first concave portion, the second convex portions are formed to surround the second concave portions and connected to one another, the second layer has through holes connecting the second concave portions and first set of the first concave portions, and the first concave portions include second set in regions opposing the second convex portions that is connected to each other.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 27, 2021
    Assignee: IBIDEN CO., LTD.
    Inventors: Masatoshi Kunieda, Hirokazu Higashi, Tatsuhiro Kawai
  • Publication number: 20190232218
    Abstract: A filter membrane includes a membrane having through holes that selectively separates specific material in processing medium, the membrane including first, second and third layers such that the first layer has first surface that is supplied with processing medium, the third layer has second surface on the opposite side of the first surface, and the second layer is formed between the first and third layers. The first layer includes first convex and concave portions, the third layer includes second convex and concave portions each having a larger area than each first concave portion, the second convex portions are formed to surround the second concave portions and connected to one another, the second layer has through holes connecting the second concave portions and first set of the first concave portions, and the first concave portions include second set in regions opposing the second convex portions that is connected to each other.
    Type: Application
    Filed: January 29, 2019
    Publication date: August 1, 2019
    Applicant: IBIDEN CO., LTD.
    Inventors: Masatoshi KUNIEDA, Hirokazu HIGASHI, Tatsuhiro KAWAI
  • Publication number: 20180154317
    Abstract: A filter membrane for selectively separating a specific material from other materials in a processing medium includes a membrane including resin material and having openings formed such that the openings selectively separate a specific material from other materials in a processing medium. The membrane has a first surface and a second surface on the opposite side with respect to the first surface such that the first surface receives the processing medium supplied to the membrane, the openings are formed through the membrane such that each of the openings has an opening part extending from the second surface toward the first surface and an expansion part expanding a size of the opening part and extending from the opening part to the first surface, and the first surface of the membrane is divided into multiple regions.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 7, 2018
    Applicant: IBIDEN CO., LTD.
    Inventors: Masatoshi Kunieda, Hirokazu Higashi
  • Patent number: 9986642
    Abstract: A method for manufacturing a printed wiring board includes forming, on a surface of an insulating layer, a patterned catalyst film including a catalyst for electroless plating such that the patterned catalyst film has a pattern corresponding to a conductor circuit, and applying electroless plating on the patterned catalyst film such that a conductor metal is deposited on the patterned catalyst film and that the conductor circuit is formed on the surface of the insulating layer.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 29, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Masatoshi Kunieda, Takafumi Okumura
  • Patent number: 9935029
    Abstract: A printed wiring board for package-on-package includes a first insulating layer, a wiring layer including a conductor pattern and formed on first surface of the first insulating layer, a second insulating layer formed on first surface side of the first insulating layer, electrodes formed in through holes of the first insulating layer respectively such that the electrodes electrically connect to the conductor pattern and have exposed surfaces exposed from second surface of the first insulating layer, first pads formed on the second insulating layer and positioned to connect an IC chip in center portion of the second insulating layer, second pads formed on the second insulating layer and positioned in outer edge portion of the second insulating layer to connect a second printed wiring board, and via conductors formed in the second insulating layer such that the via conductors electrically connect the first and second pads to the conductor pattern.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: April 3, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Takashi Kariya, Shigeru Yamada, Masatoshi Kunieda
  • Patent number: 9706663
    Abstract: A printed wiring board includes a first resin insulating layer, a first conductor pattern including first mounting pads formed on the first resin insulating layer, and a wiring structure positioned on the first resin insulating layer and including a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes second mounting pads. The second mounting pads are embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 11, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Hajime Sakamoto, Masatoshi Kunieda, Makoto Terui, Takashi Kariya
  • Patent number: 9613893
    Abstract: A wiring substrate includes a first outermost conductor layer, a first outermost insulating layer covering the first conductor layer, a second outermost conductor layer formed on opposite side of the first conductor layer, and a second outermost insulating layer covering the second conductor layer. The first insulating layer has first openings such that the first openings are exposing first conductor pads including portions of the first conductor layer, the second insulating layer has second openings such that the second openings are exposing second conductor pads including portions of the second conductor layer, each of the first conductor pads has a first plating layer recessed with respect to outer surface of the first insulating layer, and each of the second conductor pads has a second plating layer formed flush with outer surface of the second insulating layer or having bump shape protruding from the outer surface of the second insulating layer.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: April 4, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Makoto Terui, Ryojiro Tominaga, Masatoshi Kunieda, Noriki Sawada
  • Patent number: 9565756
    Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer, a second insulation layer formed on the first insulation layer and the first conductive patterns and having an opening portion, a wiring structure accommodated in the opening portion of the second insulation layer and including an insulation layer and conductive patterns on the insulation layer, second conductive patterns formed on the second insulation layer; and a via conductor formed in the second insulation layer and connecting one of the first conductive patterns and one of the second conductive patterns.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: February 7, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Makoto Terui, Daiki Komatsu, Masatoshi Kunieda
  • Publication number: 20170027057
    Abstract: A method for manufacturing a printed wiring board includes forming, on a surface of an insulating layer, a patterned catalyst film including a catalyst for electroless plating such that the patterned catalyst film has a pattern corresponding to a conductor circuit, and applying electroless plating on the patterned catalyst film such that a conductor metal is deposited on the patterned catalyst film and that the conductor circuit is formed on the surface of the insulating layer.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 26, 2017
    Applicant: IBIDEN CO., LTD.
    Inventors: Masatoshi KUNIEDA, Takafumi OKUMURA
  • Patent number: 9532468
    Abstract: A wiring board includes a first resin insulating layer, conductor pads on the first insulating layer including first and second conductor pads, a second resin insulating layer on the first insulating layer covering the first and second pads, an outermost conductor layer on the second insulating layer including first and second outermost wiring layers, via conductors through the second insulating layer including a first via conductor connecting the first wiring layer and first pad and a second via conductor connecting the second wiring layer and second pad, and a solder resist layer on the second insulating layer such that the solder resist layer is covering the first wiring layer and has one or more openings exposing the second wiring layer. The first wiring layer includes first main metal, and the second wiring layer includes second main metal which is different from the first metal of the first wiring layer.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: December 27, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Masatoshi Kunieda, Makoto Terui, Ryoujiro Tominaga, Takashi Kariya
  • Publication number: 20160268188
    Abstract: A printed wiring board for package-on-package includes a first insulating layer, a wiring layer including a conductor pattern and formed on first surface of the first insulating layer, a second insulating layer formed on first surface side of the first insulating layer, electrodes formed in through holes of the first insulating layer respectively such that the electrodes electrically connect to the conductor pattern and have exposed surfaces exposed from second surface of the first insulating layer, first pads formed on the second insulating layer and positioned to connect an IC chip in center portion of the second insulating layer, second pads formed on the second insulating layer and positioned in outer edge portion of the second insulating layer to connect a second printed wiring board, and via conductors formed in the second insulating layer such that the via conductors electrically connect the first and second pads to the conductor pattern.
    Type: Application
    Filed: February 29, 2016
    Publication date: September 15, 2016
    Applicant: IBIDEN CO., LTD.
    Inventors: Takashi KARIYA, Shigeru YAMADA, Masatoshi KUNIEDA
  • Patent number: 9433085
    Abstract: An electronic component includes an insulation layer, an alignment mark positioned on a first surface of the insulation layer, and an adhesive layer including an optically opaque agent and formed on the first surface of the insulation layer or a second surface of the insulation layer on the opposite side with respect to the first surface of the insulation layer. The adhesive layer has an opening portion formed at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: August 30, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Yoshinori Shizuno, Makoto Terui, Masatoshi Kunieda, Asuka Ii
  • Patent number: 9431347
    Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and having a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and form a distance between adjacent first and third mounting pads which is greater than a distance between adjacent first mounting pads.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: August 30, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Masatoshi Kunieda, Makoto Terui, Asuka Il, Yoshinori Shizuno
  • Patent number: 9425159
    Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and including a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and are set off from the second mounting pads toward the semiconductor element.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: August 23, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Makoto Terui, Masatoshi Kunieda, Yoshinori Shizuno, Asuka Il
  • Patent number: 9338886
    Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 10, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Toshiki Furutani, Daiki Komatsu, Masatoshi Kunieda, Naomi Fujita, Nobuya Takahashi
  • Publication number: 20160100484
    Abstract: A printed wiring board includes a base insulating layer including an insulating material, a conductor layer formed on the base insulating layer and including conductor pads, a coating insulating layer formed on the base insulating layer such that the coating insulating layer is covering the conductor layer and having opening portions exposing the conductor pads, respectively, and bumps formed on the conductor pads respectively such that each of the bumps includes an electroless plating metal layer formed on a respective one of the conductor pads and a solder layer formed on the electroless plating metal layer, the electroless plating metal layer having an upper end surface formed such that a central portion of the upper end surface is recessed relative to a peripheral portion of the upper end surface.
    Type: Application
    Filed: October 5, 2015
    Publication date: April 7, 2016
    Applicant: IBIDEN CO., LTD.
    Inventors: Masatoshi KUNIEDA, Katsuhiko TANNO
  • Publication number: 20160100482
    Abstract: A printed wiring board includes a resin insulating layer, a conductor layer formed on the resin insulating layer and including conductor pads, a solder resist layer formed on the resin insulating layer such that the solder resist layer is covering the conductor layer and has opening portions exposing the conductor pads, respectively, and metal posts formed on the conductor pads such that each of the metal posts is protruding from the solder resist layer and has a side surface forming an angle with respect to a surface of the solder resist layer.
    Type: Application
    Filed: October 5, 2015
    Publication date: April 7, 2016
    Applicant: IBIDEN CO., LTD.
    Inventor: Masatoshi Kunieda
  • Publication number: 20160066422
    Abstract: A printed wiring board includes a first resin insulating layer, a first conductor pattern including first mounting pads formed on the first resin insulating layer, and a wiring structure positioned on the first resin insulating layer and including a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes second mounting pads. The second mounting pads are embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 3, 2016
    Applicant: IBIDEN CO., LTD.
    Inventors: Hajime Sakamoto, Masatoshi Kunieda, Makoto Terui, Takashi Kariya