Patents by Inventor Masatoshi Kunieda
Masatoshi Kunieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160020164Abstract: A wiring substrate includes a first outermost conductor layer, a first outermost insulating layer covering the first conductor layer, a second outermost conductor layer formed on opposite side of the first conductor layer, and a second outermost insulating layer covering the second conductor layer. The first insulating layer has first openings such that the first openings are exposing first conductor pads including portions of the first conductor layer, the second insulating layer has second openings such that the second openings are exposing second conductor pads including portions of the second conductor layer, each of the first conductor pads has a first plating layer recessed with respect to outer surface of the first insulating layer, and each of the second conductor pads has a second plating layer formed flush with outer surface of the second insulating layer or having bump shape protruding from the outer surface of the second insulating layer.Type: ApplicationFiled: July 15, 2015Publication date: January 21, 2016Applicant: IBIDEN CO., LTD.Inventors: Makoto TERUI, Ryojiro Tominaga, Masatoshi Kunieda, Noriki Sawada
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Publication number: 20150264817Abstract: A method for manufacturing a wiring board includes positioning on a first insulation layer a wiring structure including an insulation layer and conductive patterns formed on the insulation layer, forming a second insulation layer on the first insulation layer and the wiring structure such that the wiring structure is interposed between the first insulation layer and the second insulation layer, forming a via conductor through the second insulation layer, and forming conductive patterns on the second insulation layer such that one of the conductive patterns on the second insulation layer is connected to the via conductor in the second insulation layer.Type: ApplicationFiled: May 28, 2015Publication date: September 17, 2015Applicant: IBIDEN CO., LTD.Inventors: Makoto TERUI, Daiki KOMATSU, Masatoshi KUNIEDA, Takashi KARIYA
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Patent number: 9066435Abstract: A wiring board includes a first insulation layer, a second insulation layer formed on the first insulation layer, a wiring structure interposed between the first insulation layer and the second insulation layer and including an insulation layer and conductive patterns formed on the insulation layer, second conductive patterns formed on the second insulation layer, and a via conductor formed through the second insulation layer and connected to one of the second conductive patterns on the second insulation layer.Type: GrantFiled: March 29, 2013Date of Patent: June 23, 2015Assignee: IBIDEN CO., LTD.Inventors: Makoto Terui, Daiki Komatsu, Masatoshi Kunieda, Takashi Kariya
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Publication number: 20150136459Abstract: A wiring board includes a first resin insulating layer, conductor pads on the first insulating layer including first and second conductor pads, a second resin insulating layer on the first insulating layer covering the first and second pads, an outermost conductor layer on the second insulating layer including first and second outermost wiring layers, via conductors through the second insulating layer including a first via conductor connecting the first wiring layer and first pad and a second via conductor connecting the second wiring layer and second pad, and a solder resist layer on the second insulating layer such that the solder resist layer is covering the first wiring layer and has one or more openings exposing the second wiring layer. The first wiring layer includes first main metal, and the second wiring layer includes second main metal which is different from the first metal of the first wiring layer.Type: ApplicationFiled: November 21, 2014Publication date: May 21, 2015Applicant: IBIDEN Co., Ltd.Inventors: Masatoshi KUNIEDA, Makoto Terui, Ryoujiro Tominaga, Takashi Kariya
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Publication number: 20150060124Abstract: A combined printed wiring board includes a multilayer printed wiring board having an outermost insulation layer, and a wiring film fixed to a portion of the outermost insulation layer of the multilayer printed wiring board. The wiring film includes dense-pitch pads formed on a semiconductor-mounting surface of the wiring film, the multilayer printed wiring board has sparse-pitch pads formed on a semiconductor-mounting surface of the multilayer printed wiring board, the dense-pitch pads are formed to facilitate electrical connection between a first semiconductor element and a second semiconductor element, and the sparse-pitch pads are formed to facilitate electrical connection between the multilayer printed wiring board and the first semiconductor element and/or the second semiconductor element.Type: ApplicationFiled: August 29, 2014Publication date: March 5, 2015Applicant: IBIDEN CO., LTD.Inventors: Makoto TERUI, Takashi KARIYA, Yoshinori SHIZUNO, Masatoshi KUNIEDA
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Publication number: 20150060127Abstract: A combined printed wiring board includes a multilayer printed wiring board, and a wiring film fixed to a surface of the multilayer printed wiring board and including a first wiring structure formed to connect multiple semiconductor elements and a second wiring structure formed to connect the multilayer printed wiring board and each of the semiconductor elements.Type: ApplicationFiled: August 29, 2014Publication date: March 5, 2015Applicant: IBIDEN CO., LTD.Inventors: Makoto Terui, Takashi Kariya, Yoshinori Shizuno, Masatoshi Kunieda
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Publication number: 20140360767Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and including a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and are set off from the second mounting pads toward the semiconductor element.Type: ApplicationFiled: June 3, 2014Publication date: December 11, 2014Applicant: IBIDEN CO., LTD.Inventors: Makoto TERUI, Masatoshi KUNIEDA, Yoshinori SHIZUNO, Asuka Il
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Publication number: 20140360759Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and having a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and form a distance between adjacent first and third mounting pads which is greater than a distance between adjacent first mounting pads.Type: ApplicationFiled: June 3, 2014Publication date: December 11, 2014Applicant: IBIDEN CO., LTD.Inventors: Masatoshi Kunieda, Makoto Terui, Asuka Il, Yoshinori Shizuno
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Publication number: 20140347837Abstract: A wiring board includes multiple insulation layers including an outermost insulation layer, a first conductive pattern formed between the insulation layers, a wiring structure positioned in the outermost insulation layer and having multiple first pads such that the first pads are positioned to connect multiple terminals of a first electronic component, respectively, and multiple second pads formed on the outermost insulation layer such that the second pads are positioned to connect terminals of a second electronic component, respectively, and are set at intervals which are greater than intervals of the first pads.Type: ApplicationFiled: May 21, 2014Publication date: November 27, 2014Applicant: IBIDEN CO., LTD.Inventors: Takashi KARIYA, Yoshinori Shizuno, Makoto Terui, Masatoshi Kunieda
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Publication number: 20140311780Abstract: An electronic component includes an insulation layer, an alignment mark positioned on a first surface of the insulation layer, and an adhesive layer including an optically opaque agent and formed on the first surface of the insulation layer or a second surface of the insulation layer on the opposite side with respect to the first surface of the insulation layer. The adhesive layer has an opening portion formed at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.Type: ApplicationFiled: April 23, 2014Publication date: October 23, 2014Applicant: IBIDEN CO., LTD.Inventors: Yoshinori SHIZUNO, Makoto TERUI, Masatoshi KUNIEDA, Asuka Il
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Publication number: 20140284820Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.Type: ApplicationFiled: June 4, 2014Publication date: September 25, 2014Applicant: IBIDEN CO., LTD.Inventors: Toshiki FURUTANI, Daiki KOMATSU, Masatoshi KUNIEDA, Naomi FUJITA, Nobuya TAKAHASHI
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Patent number: 8785255Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.Type: GrantFiled: February 12, 2014Date of Patent: July 22, 2014Assignee: Ibiden Co., Ltd.Inventors: Toshiki Furutani, Daiki Komatsu, Masatoshi Kunieda, Naomi Fujita, Nobuya Takahashi
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Publication number: 20140162411Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.Type: ApplicationFiled: February 12, 2014Publication date: June 12, 2014Applicant: IBIDEN CO., LTD.Inventors: Toshiki FURUTANI, Daiki Komatsu, Masatoshi Kunieda, Naomi Fujita, Nobuya Takahashi
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Publication number: 20140102768Abstract: A wiring board includes a first insulation layer, a first conductive pattern structure formed on the first insulation layer, a wiring structure formed on the first insulation layer and including a second insulation layer and a second conductive pattern structure on the second insulation layer, and a third insulation layer formed on the first insulation layer and the first conductive pattern structure and having first and second openings such that the first opening is exposing at least a portion of a surface of the wiring structure and the second opening is exposing at least a portion of the first conductive pattern structure. The wiring structure includes a third conductive pattern structure forming an outermost layer of the wiring structure and including a mounting pad structure which mounts a semiconductor device. The first opening is formed such that the first opening is exposing pad formation area of the mounting pad structure.Type: ApplicationFiled: October 15, 2013Publication date: April 17, 2014Applicant: IBIDEN CO., LTD.Inventors: Yoshinori SHIZUNO, Makoto Terui, Masatoshi Kunieda, Takashi Kariya
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Patent number: 8698303Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.Type: GrantFiled: September 30, 2011Date of Patent: April 15, 2014Assignee: Ibiden Co., Ltd.Inventors: Toshiki Furutani, Daiki Komatsu, Masatoshi Kunieda, Naomi Fujita, Nobuya Takahashi
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Publication number: 20130258625Abstract: A wiring board includes a first insulation layer, a second insulation layer formed on the first insulation layer, a wiring structure interposed between the first insulation layer and the second insulation layer and including an insulation layer and conductive patterns formed on the insulation layer, second conductive patterns formed on the second insulation layer, and a via conductor formed through the second insulation layer and connected to one of the second conductive patterns on the second insulation layer.Type: ApplicationFiled: March 29, 2013Publication date: October 3, 2013Applicant: IBIDEN CO., LTD.Inventors: Makoto Terui, Daiki Komatsu, Masatoshi Kunieda, Takashi Kariya
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Publication number: 20130256000Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer, a second insulation layer formed on the first insulation layer and the first conductive patterns and having an opening portion, a wiring structure accommodated in the opening portion of the second insulation layer and including an insulation layer and conductive patterns on the insulation layer, second conductive patterns formed on the second insulation layer; and a via conductor formed in the second insulation layer and connecting one of the first conductive patterns and one of the second conductive patterns.Type: ApplicationFiled: March 29, 2013Publication date: October 3, 2013Applicant: IBIDEN CO., LTD.Inventors: Makoto TERUI, Daiki Komatsu, Masatoshi Kunieda
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Patent number: 8546922Abstract: A wiring board including a core substrate made of an insulative material and having a penetrating portion, a first interlayer insulation layer formed on the surface of the core substrate, a first conductive circuit formed on the surface of the first interlayer insulation layer, a first via conductor formed in the first interlayer insulation layer, and an electronic component accommodated in the penetrating portion of the core substrate and including a semiconductor element, a bump body mounted on the semiconductor element, a conductive circuit connected to the bump body, an interlayer resin insulation layer formed on the conductive circuit, and a via conductor formed in the interlayer resin insulation layer. The first via conductor has a tapering direction which is opposite of a tapering direction of the via conductor in the electronic component.Type: GrantFiled: September 28, 2011Date of Patent: October 1, 2013Assignee: Ibiden Co., Ltd.Inventors: Toshiki Furutani, Daiki Komatsu, Nobuya Takahashi, Masatoshi Kunieda, Naomi Fujita, Koichi Tsunoda, Minetaka Oyama, Toshimasa Yano
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Patent number: 8487192Abstract: A printed wiring board including an insulation layer made of a resin material and having first and second surfaces, the insulation layer having an opening portion opened on the second surface, a conductive circuit having first and second surfaces, the conductive circuit being embedded in the insulation layer such that the first surface of the conductive circuit is formed flush with the first surface of the insulation layer and that the second surface of the conductive circuit is exposed through the opening portion of the insulation layer, a first surface-treatment film formed on the conductive circuit and facing the first surface of the conductive circuit, and a second surface-treatment film formed on the conductive circuit and facing the second surface of the conductive circuit and in the opening portion of the insulation layer.Type: GrantFiled: November 16, 2010Date of Patent: July 16, 2013Assignee: Ibiden Co., Ltd.Inventors: Masatoshi Kunieda, Kazuhiro Yoshikawa, Takeshi Furusawa
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Publication number: 20120181708Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.Type: ApplicationFiled: September 30, 2011Publication date: July 19, 2012Applicant: IBIDEN CO., LTD.Inventors: Toshiki FURUTANI, Daiki Komatsu, Masatoshi Kunieda, Naomi Fujita, Nobuya Takahashi