Patents by Inventor Masatoshi Yasunaga
Masatoshi Yasunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110076800Abstract: The reliability of a semiconductor device is improved. A sealing resin (sealed body) is formed between a sub-substrate (first base member) and a base substrate (second base member) that are provided individually and distinctly to be integrated therewith, and then, the sub-substrate is electrically coupled to the second base member. As a means for electrically coupling the sub-substrate to the base substrate, lands (first lands) formed on the sub-substrate and lands (second lands) formed on the base substrate are disposed such that the respective positions thereof are aligned. After through holes are formed from the lands of the sub-substrate toward the lands of the base substrate, a solder member (conductive member) is formed in each of the through holes.Type: ApplicationFiled: July 13, 2010Publication date: March 31, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuya HIRAI, Tomoaki HASHIMOTO, Takashi KIKUCHI, Masatoshi YASUNAGA, Michiaki SUGIYAMA
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Publication number: 20110074019Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.Type: ApplicationFiled: September 23, 2010Publication date: March 31, 2011Inventors: Masatoshi YASUNAGA, Hironori Matsushima, Kenya Hironaga, Soshi Kuroda
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Publication number: 20100320623Abstract: A multi-pin semiconductor device with improved reliability. In a multi-pin BGA, a plurality of wires for electrically coupling a semiconductor chip and a wiring substrate include a plurality of short and thin first wires located in an inner position and a plurality of second wires longer and thicker than the first wires. Since resin flows in from between thin first wires during resin molding, the resin pushes out air, thereby suppressing formation of voids. The reliability of the multi-pin BGA is thus improved.Type: ApplicationFiled: June 2, 2010Publication date: December 23, 2010Inventors: Soshi Kuroda, Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga
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Patent number: 6856028Abstract: In a semiconductor device, a semiconductor element is bonded to an insulating circuit board. A resin layer for bonding the semiconductor element to the insulating circuit board is extended so as to become greater in size than the semiconductor element. Further, the surroundings of the semiconductor element are sealed with resin. Reliability of mounting is improved by alleviating stress developing in a solder joint of the external electrodes of the circuit board.Type: GrantFiled: September 20, 2000Date of Patent: February 15, 2005Assignee: Renesas Technology Corp.Inventors: Kazuyuki Nakagawa, Michitaka Kimura, Masatoshi Yasunaga
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Patent number: 6768516Abstract: The invention is intended for rendering a CMOS camera compact and less costly. A semiconductor device constituting a CMOS camera system includes a lens unit which includes a wiring board having an image pick-up opening formed therein and a lens, and the lens is provided on one side of the wiring board and positioned opposite the image pick-up opening. An image pick-up semiconductor is provided on the other side of the wiring board, and is positioned opposite the image pick-up opening, and is connected to a connection section of the wiring board by means of flip-chip bonding. An image processing semiconductor is connected by means of flip-chip bonding to another connection section provided on the other side of the wiring board, and processes an image signal output from the image pick-up semiconductor.Type: GrantFiled: December 11, 2000Date of Patent: July 27, 2004Assignee: Renesas Technology Corp.Inventors: Satoshi Yamada, Michitaka Kimura, Naoto Ueda, Masatoshi Yasunaga
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Patent number: 6544814Abstract: A plurality of semiconductor chips are mounted on an insulating substrate with bumps and through use of dielectric resin for mounting purposes. The semiconductor chips are sealed with transfer mold resin through a single operation while remaining on the insulating substrate. Then, the plurality of semiconductor chips are separated together with the insulating substrate and the mounting resin into individual semiconductor devices. The productivity and reliability of packaged semiconductor devices is improved.Type: GrantFiled: January 31, 2000Date of Patent: April 8, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Yasunaga, Michitaka Kimura, Satoshi Yamada
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Publication number: 20030011053Abstract: The present invention provides a semiconductor device comprising a substrate, a semiconductor chip mounted on the substrate, external electrodes placed on the back of the substrate and for connecting electrodes of the semiconductor chip to the outside, a sealing member for encapsulating the semiconductor chip on the substrate, and a heat sink plate fixed with the sealing member. In the semiconductor device, the heat sink plate is disposed so as to be opposed to a main surface on which semiconductor elements of the semiconductor chip are formed.Type: ApplicationFiled: January 29, 2002Publication date: January 16, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Masatoshi Yasunaga
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Patent number: 6476502Abstract: An insulating resin sheet made from a thermosetting resin is provided on an insulating substrate in such a manner as to cover bonding pads provided on the insulating substrate. A lower chip is set on the insulating substrate in such a manner that bonding bumps connected to inner connection terminals of the lower chip break the insulating resin sheet 24 to be in contact with the bonding pads. The insulating resin sheet is thermally cured and subsequently the bonding bumps are melted.Type: GrantFiled: March 2, 2000Date of Patent: November 5, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Yamada, Michitaka Kimura, Masatoshi Yasunaga
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Patent number: 6469395Abstract: A semiconductor device has a first semiconductor chip 2a, a wiring substrate 1 connected to the first semiconductor chip 2a, a first surrounding substrate 6a which has an opening at a position avoiding the first semiconductor chip 2a and which is connected onto the wiring substrate 1 by flip-chip bonding, and a second semiconductor chip 2b connected onto the first surrounding substrate 2a by flip-chip bonding. A second surrounding substrate 6b comprising a two or more number of substrate elements is used for the first surrounding substrate 6a.Type: GrantFiled: May 9, 2000Date of Patent: October 22, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tatsuto Nishihara, Masatoshi Yasunaga
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Patent number: 6462425Abstract: A semiconductor device allowing a mounting of a semiconductor substrate with narrow electrode pad interval on an insulated circuit board while securing a favorable insulation characteristic and a manufacturing method thereof are obtained. The semiconductor device includes an electrode pad formed on a semiconductor substrate; a connecting underlying metal film connected to the electrode pad; a connecting conductor establishing electrical conduction between the connecting underlying metal film and a terminal electrode on an insulated circuit board; and non-conductive resin surrounding the connecting conductor and filling a gap between the substrate and the insulated circuit board.Type: GrantFiled: October 29, 1999Date of Patent: October 8, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshihiro Iwasaki, Masatoshi Yasunaga, Satoshi Yamada, Kozo Harada, Michitaka Kimura
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Publication number: 20010050717Abstract: The invention is intended for rendering a CMOS camera compact and less costly. A semiconductor device constituting a CMOS camera system includes a lens unit which includes a wiring board having an image pick-up opening formed therein and a lens, and the lens is provided on one side of the wiring board and positioned opposite the image pick-up opening. An image pick-up semiconductor is provided on the other side of the wiring board, and is positioned opposite the image pick-up opening, and is connected to a connection section of the wiring board by means of flip-chip bonding. An image processing semiconductor is connected by means of flip-chip bonding to another connection section provided on the other side of the wiring board, and processes an image signal output from the image pick-up semiconductor.Type: ApplicationFiled: December 11, 2000Publication date: December 13, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Yamada, Michitaka Kimura, Naoto Ueda, Masatoshi Yasunaga
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Publication number: 20010042863Abstract: An insulating resin sheet made from a thermosetting resin is provided on an insulating substrate in such a manner as to cover bonding pads provided on the insulating substrate. A lower chip is set on the insulating substrate in such a manner that bonding bumps connected to inner connection terminals of the lower chip break the insulating resin sheet 24 to be in contact with the bonding pads. The insulating resin sheet is thermally cured and subsequently the bonding bumps are melted.Type: ApplicationFiled: March 2, 2000Publication date: November 22, 2001Inventors: Satoshi Yamada, Michitaka Kimura, Masatoshi Yasunaga
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Patent number: 6256875Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.Type: GrantFiled: September 22, 1999Date of Patent: July 10, 2001Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Masaki Watanabe, Akiyoshi Sawai, Yoshikazu Narutaki, Tomoaki Hashimoto, Masatoshi Yasunaga, Jun Shibata, Hiroshi Seki, Kazuhiko Kurafuchi, Katsunori Asai
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Patent number: 6191493Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.Type: GrantFiled: March 2, 1999Date of Patent: February 20, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Yasunaga, Shin Nakao, Shinji Baba, Mitsuyasu Matsuo, Hironori Matsushima
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Patent number: 6005289Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.Type: GrantFiled: October 24, 1996Date of Patent: December 21, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Masaki Watanabe, Akiyoshi Sawai, Yoshikazu Narutaki, Tomoaki Hashimoto, Masatoshi Yasunaga, Jun Shibata, Hiroshi Seki, Kazuhiko Kurafuchi, Katsunori Asai
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Patent number: 5920770Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.Type: GrantFiled: April 14, 1997Date of Patent: July 6, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Yasunaga, Shin Nakao, Shinji Baba, Mitsuyasu Matsuo, Hironori Matsushima
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Patent number: 5753973Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.Type: GrantFiled: February 11, 1997Date of Patent: May 19, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Yasunaga, Shin Nakao, Shinji Baba, Mitsuyasu Matsuo, Hironori Matsushima
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Patent number: 5656863Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.Type: GrantFiled: February 17, 1994Date of Patent: August 12, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Yasunaga, Shin Nakao, Shinji Baba, Mitsuyasu Matsuo, Hironori Matsushima
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Patent number: 5296710Abstract: An infrared radiation detector so adapted as to prevent the image signals from deteriorating due to the short length of leads extending within the cryogenic container with the infrared radiation sensing element accommodated within and to correspond to the increasing number of the leads and terminals, associated with a high density of elements. The infrared radiation detector is composed of an inner cylinder and an outer cylinder. The outer cylinder is disposed so as to lie in the same plane as the sub-package on which the multi-layered ceramic lead plate composed of a plurality of bonding pads for wire bonding, internally embedded lead layers, and plug-in terminals for fetching signals is mounted. The bonding pad of the sub-package is bonded to the bonding pad of the ceramic lead plate through a wire bonding.Type: GrantFiled: April 15, 1992Date of Patent: March 22, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuhiro Ohno, Akifumi Wada, Yousuke Sugiura, Masatoshi Yasunaga
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Patent number: 5217910Abstract: First, a low-concentration impurity layer is formed by obliquely implanting an n-type impurity at a prescribed angle with respect to the surface of a p-type semiconductor substrate, using a gate electrode formed on the semiconductor substrate as a mask. Thereafter a sidewall spacer is formed on the sidewall of the gate electrode, and then a medium-concentration impurity layer is formed by obliquely implanting an n-type impurity to the surface of the semiconductor substrate. Thereafter a high-concentration impurity layer is formed by substantially perpendicularly implanting an n-type impurity with respect to the surface of the semiconductor substrate. According to this method, the low-concentration impurity layer in source and drain regions having triple diffusion structures can be accurately overlapped with the gate electrode, with no requirement for heat treatment for thermal diffusion.Type: GrantFiled: October 24, 1991Date of Patent: June 8, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masahiro Shimizu, Katsuyoshi Mitsui, Yomiyuki Yama, Masatoshi Yasunaga