Patents by Inventor Masaya Katayama

Masaya Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200127107
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor area of a first conductive type disposed in a surface layer portion of the semiconductor substrate, a gate electrode disposed over the first semiconductor area and extending in a first direction, a dummy gate electrode disposed over the semiconductor substrate away from the gate electrode and extending in the first direction, a second semiconductor area of a second conductive type disposed, in the surface layer portion of the semiconductor substrate, between the gate electrode and the dummy gate electrode, and an interconnect connected to the second semiconductor area, wherein a concentration of carrier of a first carrier type in the semiconductor substrate under the dummy gate electrode and alongside the second semiconductor area is lower than a concentration of majority carrier in the first semiconductor area, the first carrier type being a same carrier type as the majority carrier.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 23, 2020
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Masaya Katayama
  • Patent number: 10300802
    Abstract: A charging system 1 including a charging apparatus 10 and a data base 20, the charging apparatus 10 including a power supply unit 11, a control unit 12, and a plurality of charging connectors 13-1 to 13-3 compliant with different charging standards. When authentication of identification information succeeds, the control unit 12 determines a charging standard on the basis of vehicle information of the data base 20 and when the authentication of the identification information fails, determines a charging standard on the basis of vehicle information input by a user. Further, the control unit 12 unlocks a charging connector compliant with the determined charging standard and notifies of unlocking.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 28, 2019
    Assignee: NICHICON CORPORATION
    Inventors: Yuki Katayama, Ryosuke Koguchi, Hiroyuki Sumimura, Masaya Nishi
  • Publication number: 20150107764
    Abstract: Provided is a process for producing an adhesive sheet having a singulated adhesive layer (b) on a carrier film (a), comprising the following steps in the order mentioned: Step A: cutting an adhesive film having a carrier film (a), an adhesive layer (b), and a cover film (c) in the order mentioned locally only at the adhesive layer (b) and the cover film (c) by means of local half-cutting; Step B: peeling only the cover film (c) at unwanted parts of the adhesive film; Step C: applying adhesive tape to the side of the cover film (c) of the adhesive film; and Step D: peeling the adhesive layer (b) at unwanted parts and the cover film (c) at desired parts of the adhesive film together with the adhesive tape. Also provided are a process for producing an adhesive sheet comprising a singulated adhesive disposed at a specific position, and equipment for producing an adhesive sheet.
    Type: Application
    Filed: June 26, 2013
    Publication date: April 23, 2015
    Applicant: TORAY INDUSTRIES, INC.
    Inventors: Masaya Katayama, Hiroyuki Niwa, Toshihisa Nonaka
  • Patent number: 8686499
    Abstract: A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A circular gate electrode is formed over a pn junction between sides of the p-type body region and the n-type drift region along the pn junction. An n-type drain region and an n-type source region are formed in the n-type drift region and the p-type body region, respectively, with a part of the gate electrode between.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 1, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masaya Katayama, Masayoshi Asano
  • Patent number: 8410533
    Abstract: A semiconductor device includes a semiconductor substrate having at least one surface provided with a semiconductor element, wherein the semiconductor substrate includes a region of a first conductivity type, the region being formed in a surface layer portion of the semiconductor substrate; a first diffusion region of a second conductivity type, the first diffusion region having a first impurity concentration and being formed in the surface layer portion, and a pn junction being formed between the first diffusion region and the region of the first conductivity type; and a first metal silicide film formed on part of a portion of the surface corresponding to the first diffusion region.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masaya Katayama
  • Patent number: 8409913
    Abstract: A semiconductor device includes a semiconductor substrate having at least one surface provided with a semiconductor element, wherein the semiconductor substrate includes a region of a first conductivity type, the region being formed in a surface layer portion of the semiconductor substrate; a first diffusion region of a second conductivity type, the first diffusion region having a first impurity concentration and being formed in the surface layer portion, and a pn junction being formed between the first diffusion region and the region of the first conductivity type; and a first metal silicide film formed on part of a portion of the surface corresponding to the first diffusion region.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masaya Katayama
  • Publication number: 20120270364
    Abstract: A semiconductor device includes a semiconductor substrate having at least one surface provided with a semiconductor element, wherein the semiconductor substrate includes a region of a first conductivity type, the region being formed in a surface layer portion of the semiconductor substrate; a first diffusion region of a second conductivity type, the first diffusion region having a first impurity concentration and being formed in the surface layer portion, and a pn junction being formed between the first diffusion region and the region of the first conductivity type; and a first metal silicide film formed on part of a portion of the surface corresponding to the first diffusion region.
    Type: Application
    Filed: June 28, 2012
    Publication date: October 25, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Masaya Katayama
  • Publication number: 20120119292
    Abstract: A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A circular gate electrode is formed over a pn junction between sides of the p-type body region and the n-type drift region along the pn junction. An n-type drain region and an n-type source region are formed in the n-type drift region and the p-type body region, respectively, with a part of the gate electrode between.
    Type: Application
    Filed: September 7, 2011
    Publication date: May 17, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaya Katayama, Masayoshi Asano
  • Publication number: 20110024807
    Abstract: A semiconductor device includes a semiconductor substrate having at least one surface provided with a semiconductor element, wherein the semiconductor substrate includes a region of a first conductivity type, the region being formed in a surface layer portion of the semiconductor substrate; a first diffusion region of a second conductivity type, the first diffusion region having a first impurity concentration and being formed in the surface layer portion, and a pn junction being formed between the first diffusion region and the region of the first conductivity type; and a first metal silicide film formed on part of a portion of the surface corresponding to the first diffusion region.
    Type: Application
    Filed: July 9, 2010
    Publication date: February 3, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Masaya Katayama
  • Patent number: 7768087
    Abstract: A photodiode formed over a silicon substrate is disclosed. The photodiode includes a light-receiving region formed of a diffusion region of a first conduction type at the surface of the silicon substrate and forming a pn junction; an intermediate region formed of a diffusion region of the first conduction type at the surface of the silicon substrate so as to be included in the light-receiving region; a contact region formed of a diffusion region of the first conduction type at the surface of the silicon substrate so as to be included in the intermediate region; a shield layer formed of a diffusion region of a second conduction type in a part of the surface of the silicon substrate outside the intermediate region; and an electrode in contact with the contact region. The shield layer faces the side end part of the diffusion region forming the intermediate region.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: August 3, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masaya Katayama
  • Publication number: 20090001496
    Abstract: A photodiode formed over a silicon substrate is disclosed. The photodiode includes a light-receiving region formed of a diffusion region of a first conduction type at the surface of the silicon substrate and forming a pn junction; an intermediate region formed of a diffusion region of the first conduction type at the surface of the silicon substrate so as to be included in the light-receiving region; a contact region formed of a diffusion region of the first conduction type at the surface of the silicon substrate so as to be included in the intermediate region; a shield layer formed of a diffusion region of a second conduction type in a part of the surface of the silicon substrate outside the intermediate region; and an electrode in contact with the contact region. The shield layer faces the side end part of the diffusion region forming the intermediate region.
    Type: Application
    Filed: February 26, 2008
    Publication date: January 1, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Masaya Katayama
  • Patent number: 7452771
    Abstract: The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control gate 18 formed of an impurity region of the first conduction type formed in the second well 16, a first impurity diffused layer 26 and a second impurity diffused layer 33 formed with a channel region 25 therebetween, and a floating gate electrode 20 formed on the channel region 25 and the control gate 18 with a gate insulation film 24 therebetween. The control gate 18 is buried in the semiconductor substrate 10, which makes it unnecessary to form the control gate 18 on the floating gate electrode 20. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: November 18, 2008
    Assignee: Fujitsu Limited
    Inventors: Masaki Ito, Masaya Katayama, Takaaki Furuyama, Shozo Kawabata
  • Patent number: 7419864
    Abstract: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: September 2, 2008
    Assignee: Fujitsu Limited
    Inventors: Narumi Ohkawa, Masaya Katayama
  • Patent number: 7341220
    Abstract: A roll support member is provided that is used for suspending in a packaging case a roll-form recording material wound around a core. The roll support member includes a four corner-cut square flange portion having a thickness and an insertion portion that projects cylindrically from substantially the center of the flange portion and is inserted into one end of the core. The flange portion and the insertion portion are formed integrally. The side of the flange portion from which the insertion portion projects is a flat face. The side of the flange portion opposite to the flat face is provided with ribs forming a plurality of energy absorbing space zones. The outer peripheral side of the flange portion has a height that is no greater than the height of the ribs. There is also provided a recording material package in which a roll-form recording material is suspended and supported in a housing by the roll support members.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: March 11, 2008
    Assignee: FUJIFILM Corporation
    Inventor: Masaya Katayama
  • Publication number: 20070281414
    Abstract: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.
    Type: Application
    Filed: August 1, 2007
    Publication date: December 6, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Narumi Ohkawa, Masaya Katayama
  • Patent number: 7285838
    Abstract: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: October 23, 2007
    Assignee: Fujitsu Limited
    Inventors: Narumi Ohkawa, Masaya Katayama
  • Publication number: 20060145286
    Abstract: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.
    Type: Application
    Filed: April 29, 2005
    Publication date: July 6, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Narumi Ohkawa, Masaya Katayama
  • Publication number: 20060046373
    Abstract: The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control gate 18 formed of an impurity region of the first conduction type formed in the second well 16, a first impurity diffused layer 26 and a second impurity diffused layer 33 formed with a channel region 25 therebetween, and a floating gate electrode 20 formed on the channel region 25 and the control gate 18 with a gate insulation film 24 therebetween. The control gate 18 is buried in the semiconductor substrate 10, which makes it unnecessary to form the control gate 18 on the floating gate electrode 20. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.
    Type: Application
    Filed: October 13, 2005
    Publication date: March 2, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masaki Ito, Masaya Katayama, Takaaki Furuyama, Shozo Kawabata
  • Patent number: 7005690
    Abstract: The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20 of a first conduction type surrounding a first region thereof; a first buried diffused layer 40c of the second conduction type buried in the first region: a second well 44b of the first conduction type formed near a surface of the semiconductor substrate 20 in the first region; and a first transistor 38e formed on the second well 44b.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: February 28, 2006
    Assignee: Fujitsu Limited
    Inventors: Masahiro Chijiiwa, Shigetoshi Takeda, Masaya Katayama
  • Publication number: 20060011956
    Abstract: The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20 of a first conduction type surrounding a first region thereof; a first buried diffused layer 40c of the second conduction type buried in the first region: a second well 44b of the first conduction type formed near a surface of the semiconductor substrate 20 in the first region; and a first transistor 38e formed on the second well 44b.
    Type: Application
    Filed: December 6, 2004
    Publication date: January 19, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Chijiiwa, Shigetoshi Takeda, Masaya Katayama