Patents by Inventor Masaya Katayama
Masaya Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060011956Abstract: The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20 of a first conduction type surrounding a first region thereof; a first buried diffused layer 40c of the second conduction type buried in the first region: a second well 44b of the first conduction type formed near a surface of the semiconductor substrate 20 in the first region; and a first transistor 38e formed on the second well 44b.Type: ApplicationFiled: December 6, 2004Publication date: January 19, 2006Applicant: FUJITSU LIMITEDInventors: Masahiro Chijiiwa, Shigetoshi Takeda, Masaya Katayama
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Patent number: 6977411Abstract: The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control gate 18 formed of an impurity region of the first conduction type formed in the second well 16, a first impurity diffused layer 26 and a second impurity diffused layer 33 formed with a channel region 25 therebetween, and a floating gate electrode 20 formed on the channel region 25 and the control gate 18 with a gate insulation film 24 therebetween. The control gate 18 is buried in the semiconductor substrate 10, which makes it unnecessary to form the control gate 18 on the floating gate electrode 20. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.Type: GrantFiled: December 18, 2003Date of Patent: December 20, 2005Assignee: Fujitsu LimitedInventors: Masaki Ito, Masaya Katayama, Takaaki Furuyama, Shozo Kawabata
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Publication number: 20040134820Abstract: A roll support member is provided that is used for suspending in a packaging case a roll-form recording material wound around a core. The roll support member includes a four corner-cut square flange portion having a thickness and an insertion portion that projects cylindrically from substantially the center of the flange portion and is inserted into one end of the core. The flange portion and the insertion portion are formed integrally. The side of the flange portion from which the insertion portion projects is a flat face. The side of the flange portion opposite to the flat face is provided with ribs forming a plurality of energy absorbing space zones. The outer peripheral side of the flange portion has a height that is no greater than the height of the ribs. There is also provided a recording material package in which a roll-form recording material is suspended and supported in a housing by the roll support members.Type: ApplicationFiled: December 24, 2003Publication date: July 15, 2004Applicant: FUJI PHOTO FILM CO., LTD.Inventor: Masaya Katayama
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Publication number: 20040129970Abstract: The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control gate 18 formed of an impurity region of the first conduction type formed in the second well 16, a first impurity diffused layer 26 and a second impurity diffused layer 33 formed with a channel region 25 therebetween, and a floating gate electrode 20 formed on the channel region 25 and the control gate 18 with a gate insulation film 24 therebetween. The control gate 18 is buried in the semiconductor substrate 10, which makes it unnecessary to form the control gate 18 on the floating gate electrode 20. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.Type: ApplicationFiled: December 18, 2003Publication date: July 8, 2004Inventors: Masaki Ito, Masaya Katayama, Takaaki Furuyama, Shozo Kawabata
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Patent number: 6533475Abstract: A pack case includes a case body, a bottom cover and a pressure plate, which are formed from plastic material. On lateral walls of the case body is provided ribs that are fit into engaging grooves formed in spaces surrounded by a bottom plate and both lateral walls of the bottom cover. The lateral walls have projections, bottom surfaces of which are inclined to fit the inclination of top surfaces of the ribs. Lateral walls of the case body are inclined such that inclination angle in an upper portion is larger than that in a lower portion. A sponge sheet for preventing deviation of an instant photo film unit is attached to the bottom cover. After inserting projections on the bottom cover into holes of the sponge sheet, the projections are deformed by pressure and heat, so that the projections are cut into the sponge sheet.Type: GrantFiled: May 22, 2001Date of Patent: March 18, 2003Assignee: Fuji Photo Film Co., Ltd.Inventor: Masaya Katayama
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Publication number: 20020111004Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.Type: ApplicationFiled: April 18, 2002Publication date: August 15, 2002Applicant: FUJITSU LIMITEDInventors: Seiichi Suzuki, Kazuhiro Adachi, Masaya Katayama, Noriyuki Suzuki, Osamu Hideshima, Kenichi Kawabata, Masaya Ohtsuki, Manabu Hayashi, Junichi Yayanagi
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Patent number: 6399472Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.Type: GrantFiled: June 11, 1999Date of Patent: June 4, 2002Assignee: Fujitsu LimitedInventors: Seiichi Suzuki, Kazuhiro Adachi, Masaya Katayama, Noriyuki Suzuki, Osamu Hideshima, Kenichi Kawabata, Masaya Ohtsuki, Manabu Hayashi, Junichi Yayanagi
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Patent number: 6326254Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.Type: GrantFiled: May 1, 1998Date of Patent: December 4, 2001Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Taiji Ema, Satoru Miyoshi, Tatsumi Tsutsui, Masaya Katayama, Masayoshi Asano, Kenichi Kanazawa
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Publication number: 20010046386Abstract: A pack case includes a case body, a bottom cover and a pressure plate, which are formed from plastic material. On lateral walls of the case body is provided ribs that are fit into engaging grooves formed in spaces surrounded by a bottom plate and both lateral walls of the bottom cover. The lateral walls have projections, bottom surfaces of which are inclined to fit the inclination of top surfaces of the ribs. Lateral walls of the case body are inclined such that inclination angle in an upper portion is larger than that in a lower portion. A sponge sheet for preventing deviation of an instant photo film unit is attached to the bottom cover. After inserting projections on the bottom cover into holes of the sponge sheet, the projections are deformed by pressure and heat, so that the projections are cut into the sponge sheet.Type: ApplicationFiled: May 22, 2001Publication date: November 29, 2001Applicant: FUJI PHOTO FILM CO., LTD.Inventor: Masaya Katayama
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Patent number: 6251743Abstract: Microstructures, including a plurality of spaced structural members which are bendable under an external force, undergo a treating method using a first treating liquid, to prevent permanent deformation, by removing the microstructure from the first treating liquid to an environment having a pressure less than atmospheric pressure; or moving the microstructure from the first treating liquid to a second treating liquid having a smaller surface tension than the first treating liquid, and then removing the microstructure from the second liquid; or drying the microstructure removed from the first treating liquid by exposing same to a liquid vapor having a smaller surface tension than the first treating liquid; or removing the microstructure from the first treating liquid to the atmosphere, and drying the microstructure using an energy beam of high intensity or an ultrasonic wave.Type: GrantFiled: May 5, 1998Date of Patent: June 26, 2001Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Motoo Nakano, Hiroshi Nomura, Masaya Katayama, Toshimi Ikeda, Fumihiko Inoue, Junichi Ishikawa, Masahiro Kuwamura
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Patent number: 6195508Abstract: An instant photo film pack has a pack body, which has a small thickness and has first and second walls opposed to each other, and contains a stack of plural self-developing photo film units. An exposure opening is formed in the first wall, and provides each of the photo film units with an exposure. An exit slit is formed in the pack body, disposed in an advancing direction, for exiting each of the photo film units. A light-shielding cover sheet closes the exposure opening in a light-tight manner, to be exited through the exit slit by an external operation. Two dimple-formed deformed portions are disposed on the light-shielding cover sheet to project toward the photo film units, and prevents a first photo film unit among the photo film units from passing the exit slit while the light-shielding cover sheet is exited, the first photo film unit being directly behind the light-shielding cover sheet.Type: GrantFiled: September 3, 1999Date of Patent: February 27, 2001Assignee: Fuji Photo Film Co., Ltd.Inventors: Masaya Katayama, Kazunori Mizuno, Nobuo Sigiyama
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Patent number: 6093943Abstract: A method of producing a semiconductor device includes the steps of (a) preparing a substrate having a semiconductor element formed in a predetermined region of a surface of the substrate, (b) forming a first layer on the substrate, where the first layer is made of silicon oxide including at least one of boron and phosphor, (c) forming a second layer on a surface of the first layer, where the second layer is made of a material selected from a group consisting of silicon nitride and silicon oxide nitride, (d) coating a resist layer on the entire surface of the substrate, (e) exposing and developing a predetermined region of the resist layer using a reticle having a first opening so as to form a second opening in the resist layer, where the first opening has a polygonal shape having n corners respectively having obtuse angles and n is a natural number satisfying n.gtoreq.5, and (f) etching the second and first layers via the second opening.Type: GrantFiled: December 28, 1998Date of Patent: July 25, 2000Assignee: Fujitsu LimitedInventors: Shinichiro Ikemasu, Taiji Ema, Masaya Katayama
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Patent number: 5907773Abstract: A method of producing a semiconductor device includes the steps of (a) preparing a substrate having a semiconductor element formed in a predetermined region of a surface of the substrate, (b) forming a first layer on the substrate, where the first layer is made of silicon oxide including at least one of boron and phosphor, (c) forming a second layer on a surface of the first layer, where the second layer is made of a material selected from a group consisting of silicon nitride and silicon oxide nitride, (d) coating a resist layer on the entire surface of the substrate, (e) exposing and developing a predetermined region of the resist layer using a reticle having a first opening so as to form a second opening in the resist layer, where the first opening has a polygonal shape having n corners respectively having obtuse angles and n is a natural number satisfying n.gtoreq.5, and (f) etching the second and first layers via the second opening.Type: GrantFiled: February 8, 1996Date of Patent: May 25, 1999Assignee: Fujitsu LimitedInventors: Shinichiro Ikemasu, Taiji Ema, Masaya Katayama
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Patent number: 5888633Abstract: A micro-structure including at least a first bendable member having first and second ends and being supported at the first end only, and either being spaced from a rigid component, or being spaced from a second bendable member also supported only at a first end thereof. The first member has a length L from the first end to the second end specified by one of the following equations: (a) for the first member adjacent to the rigid component: L<(2Edt.sup.3 /3P).sup.1/4, wherein E is a Young's modulus of a material of the first member; d is a distance of the space between the first member and the rigid component; t is a thickness of the first member; and P is an external pressure applied to the first member; or b) for the first member adjacent to the second member: L<(2Ed't.sup.3 /3P).sup.1/4, wherein E, t and P are as defined above; and d' is a distance of the space between the first and second members.Type: GrantFiled: March 12, 1997Date of Patent: March 30, 1999Assignee: Fujitsu Limited & Fujitsu VLSI LimitedInventors: Motoo Nakano, Hiroshi Nomura, Masaya Katayama, Toshimi Ikeda, Fumihiko Inoue, Junichi Ishikawa, Masahiro Kuwamura
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Patent number: 5789788Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.Type: GrantFiled: November 20, 1996Date of Patent: August 4, 1998Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Taiji Ema, Satoru Miyoshi, Tatsumi Tsutsui, Masaya Katayama, Masayoshi Asano, Kenichi Kanazawa
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Patent number: 5661340Abstract: A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.Type: GrantFiled: October 26, 1993Date of Patent: August 26, 1997Assignee: Fujitsu LimitedInventors: Taiji Ema, Masaaki Higashitani, Toshimi Ikeda, Michiari Kawano, Hiroshi Nomura, Masaya Katayama, Masahiro Kuwamura
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Patent number: 5652167Abstract: Micro-structures comprising at least a structural member, which is liable to be bent under an external force and formed so as to leave a space between the member and another member liable to be bent and/or other rigid component, are successfully treated using a treating liquid, without suffering permanent deformation resulting from the use of the treating liquid, by removing the micro-structures from the liquid to an environment having a pressure less than the atmospheric pressure; or displacing the micro-structures from the treating liquid to another treating liquid having a smaller surface tension than that of the former liquid, and then removing the micro-structures from the latter liquid; or drying the micro-structures removed from the treating liquid by exposing the same to vapor of a liquid having a smaller surface tension than that of the treating liquid; or removing the micro-structures from the treating liquid to the atmosphere, and drying them using an energy beam of high intensity or an ultrasonicType: GrantFiled: June 29, 1993Date of Patent: July 29, 1997Assignees: Fujitsu Ltd., Fujitsu VLSI Ltd.Inventors: Motoo Nakano, Hiroshi Nomura, Masaya Katayama, Toshimi Ikeda, Fumihiko Inoue, Junichi Ishikawa, Masahiro Kuwamura
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Patent number: 5561314Abstract: A method of manufacturing a semiconductor device capable of isolating fine pattern elements by using LOCOS. The method includes the steps of: (a) forming a relatively thick first nitride film pattern on the surface of a semiconductor substrate having an oxide film; (b) wet-etching the oxide film by using the first nitride film as a mask; (c) filling the under-etch region of the first nitride film with nitride and forming a second nitride film thinner than the first nitride film on the exposed surface of the semiconductor substrate; (d) thermally oxidizing all the exposed second nitride film in a dry oxygen atmosphere to form an oxide film on the surface of the semiconductor substrate at least at the region not covered with the first nitride film; and (e) forming a thermal oxide film on the semiconductor substrate not covered with the first nitride film at a temperature lower than the oxidation temperature at the step (d).Type: GrantFiled: June 5, 1995Date of Patent: October 1, 1996Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Taiji Ema, Masaya Katayama
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Patent number: 5525534Abstract: A method of producing a semiconductor device includes the steps of (a) preparing a substrate having a semiconductor element formed in a predetermined region of a surface of the substrate, (b) forming a first layer on the substrate, where the first layer is made of silicon oxide including at least one of boron and phosphor, (c) forming a second layer on a surface of the first layer, where the second layer is made of a material selected from a group consisting of silicon nitride and silicon oxide nitride, (d) coating a resist layer on the entire surface of the substrate, (e) exposing and developing a predetermined region of the resist layer using a reticle having a first opening so as to form a second opening in the resist layer, where the first opening has a polygonal shape having n corners respectively having obtuse angles and n is a natural number satisfying n.gtoreq.5, and (f) etching the second and first layers via the second opening.Type: GrantFiled: January 5, 1995Date of Patent: June 11, 1996Assignee: Fujitsu LimitedInventors: Shinichiro Ikemasu, Taiji Ema, Masaya Katayama
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Patent number: 5453397Abstract: A method of manufacturing a semiconductor device capable of isolating fine pattern elements by using LOCOS. The method includes the steps of: (a) forming a relatively thick first nitride film pattern on the surface of a semiconductor substrate having an oxide film; (b) wet-etching the oxide film by using the first nitride film as a mask; (c) filling the under-etch region of the first nitride film with nitride and forming a second nitride film thinner than the first nitride film on the exposed surface of the semiconductor substrate; (d) thermally oxidizing all the exposed second nitride film in a dry oxygen atmosphere to form an oxide film on the surface of the semiconductor substrate at least at the region not covered with tile first nitride film; and (e) forming a thermal oxide film on the semiconductor substrate not covered with the first nitride film at a temperature lower than the oxidation temperature at the step (d).Type: GrantFiled: September 12, 1994Date of Patent: September 26, 1995Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Taiji Ema, Masaya Katayama