Patents by Inventor Masaya Kawano

Masaya Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220371254
    Abstract: The present rotary extruder includes: a rotor having a cylindrical surface centered on a rotor axis extending in a horizontal direction; and a casing having an inner peripheral surface that defines a bore, wherein: the casing defines an input port into which a resin material including a thermoplastic resin is fed, and a discharge port from which a plasticized molten resin is discharged; the cylindrical surface of the rotor and the inner peripheral surface of the casing are arranged eccentric with each other, thereby forming a gap whose cross section is crescent-shaped, extending in a rotation direction of the rotor from the input port to the discharge port between the inner peripheral surface and the cylindrical surface; and the input port is arranged at a top portion of the casing and the discharge port is arranged at a lower portion of the casing.
    Type: Application
    Filed: September 25, 2020
    Publication date: November 24, 2022
    Inventors: Masaya OOUE, Takayoshi KAWANO
  • Publication number: 20220316523
    Abstract: A fluid film bearing includes a plurality of bearing pads that are arranged in a circumferential direction of a rotating body that rotates about an axis, and that support the rotating body via a fluid film, wherein the bearing pad includes a base layer made of metal, an elastic layer that is layered on the rotating body side of the base layer, and that is made of an elastically deformable elastic material, a sliding layer that is layered on the rotating body side of the elastic layer, and that opposes the rotating body and is made of a bearing material, and a metal plate that is layered between the elastic layer and the sliding layer, and that is more rigid than the elastic layer and the sliding layer.
    Type: Application
    Filed: March 15, 2022
    Publication date: October 6, 2022
    Inventors: Yoshitomo NODA, Takuzo SHIGIHARA, Shimpei YOKOYAMA, Chihiro YOSHIMINE, Masaya KAWANO
  • Publication number: 20220107228
    Abstract: A temperature measuring device includes an ultrasonic sensor attached to a rear surface side of the structural body having the multilayer structure, an acquisition unit configured to, through the ultrasonic sensor, acquire a signal of a reflected wave of an ultrasonic wave incident at the internal side of the structural body, an extraction unit configured to extract, from the signal of the reflected wave, a domain including a reflected wave reflected on a surface on the internal side of the structural body, and an identification unit configured to, based on a signal of the reflected wave in the extracted domain, identify the temperature of the surface on the internal side of the structural body.
    Type: Application
    Filed: June 21, 2021
    Publication date: April 7, 2022
    Inventors: Masaya KAWANO, Masahiro SUGIHARA, Tadashi KIMURA, Shinsuke SATO
  • Patent number: 10879227
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 29, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Patent number: 10720339
    Abstract: A fan-out wafer-level packaging method and the package produced thereof are provided in the present application.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 21, 2020
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Masaya Kawano, Ka Fai Chang
  • Publication number: 20200118994
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 10580763
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 3, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20190393051
    Abstract: A fan-out wafer-level packaging method and the package produced thereof are provided in the present application.
    Type: Application
    Filed: April 27, 2017
    Publication date: December 26, 2019
    Inventors: Masaya KAWANO, Ka Fai Chang
  • Publication number: 20190139953
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 9, 2019
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 10224318
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Patent number: 9978512
    Abstract: A circuit device, includes a semiconductor substrate, and a first inductor provided over said semiconductor substrate, and a first interconnect provided over said semiconductor substrate and coupled with first inductor.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 22, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaya Kawano, Yasutaka Nakashiba
  • Publication number: 20180019237
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 18, 2018
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 9847325
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 19, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20170236810
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: November 17, 2016
    Publication date: August 17, 2017
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Publication number: 20170053738
    Abstract: A circuit device, includes a semiconductor substrate, and a first inductor provided over said semiconductor substrate, and a first interconnect provided over said semiconductor substrate and coupled with first inductor.
    Type: Application
    Filed: November 9, 2016
    Publication date: February 23, 2017
    Inventors: Masaya KAWANO, Yasutaka NAKASHIBA
  • Patent number: 9524953
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 20, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Patent number: 9502175
    Abstract: A circuit device includes a semiconductor substrate, a first inductor provided over the semiconductor substrate, and a second inductor provided over the semiconductor substrate and coupled to the first inductor. The first inductor and second inductor are wound in a same direction with each other from respective inner end portions to respective outer end portions thereof.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: November 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Masaya Kawano, Yasutaka Nakashiba
  • Publication number: 20160307875
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 9406602
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: August 2, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20150137348
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: January 27, 2015
    Publication date: May 21, 2015
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA