Patents by Inventor Masaya Kawano
Masaya Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953384Abstract: A temperature measuring device includes an ultrasonic sensor attached to a rear surface side of the structural body having the multilayer structure, an acquisition unit configured to, through the ultrasonic sensor, acquire a signal of a reflected wave of an ultrasonic wave incident at the internal side of the structural body, an extraction unit configured to extract, from the signal of the reflected wave, a domain including a reflected wave reflected on a surface on the internal side of the structural body, and an identification unit configured to, based on a signal of the reflected wave in the extracted domain, identify the temperature of the surface on the internal side of the structural body.Type: GrantFiled: June 21, 2021Date of Patent: April 9, 2024Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Masaya Kawano, Masahiro Sugihara, Tadashi Kimura, Shinsuke Sato
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Publication number: 20230341056Abstract: This seal device comprises: a movable seal ring arranged so as to be deformable in the radial direction, in a state of facing an outer peripheral surface of a rotor of a steam turbine capable of rotating around the axis; a first elastic member provided to each of end surfaces of the movable seal ring in the circumferential direction; and a second elastic member that is provided to an intermediate position in the circumferential direction of the movable seal ring and urges the movable seal ring outward in the radial direction.Type: ApplicationFiled: September 14, 2021Publication date: October 26, 2023Inventors: Norihisa TAKEI, Hidekazu UEHARA, Takumi HORI, Kohei OZAKI, Azumi YOSHIDA, Masaya KAWANO, Shin NISHIMOTO, Tatsuro FURUSHO, Shintaro OKUMURA
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Patent number: 11795997Abstract: A fluid film bearing includes a plurality of bearing pads that are arranged in a circumferential direction of a rotating body that rotates about an axis, and that support the rotating body via a fluid film, wherein the bearing pad includes a base layer made of metal, an elastic layer that is layered on the rotating body side of the base layer, and that is made of an elastically deformable elastic material, a sliding layer that is layered on the rotating body side of the elastic layer, and that opposes the rotating body and is made of a bearing material, and a metal plate that is layered between the elastic layer and the sliding layer, and that is more rigid than the elastic layer and the sliding layer.Type: GrantFiled: March 15, 2022Date of Patent: October 24, 2023Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Yoshitomo Noda, Takuzo Shigihara, Shimpei Yokoyama, Chihiro Yoshimine, Masaya Kawano
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Publication number: 20230258268Abstract: A sealing device is disposed between a stationary body and a rotating body and is configured to suppress flow of a fluid from a high-pressure side to a low-pressure side. The sealing device includes: a sealing member movably supported by the stationary body in an axial direction and a radial direction of the rotating body; a seal fin extending from the sealing member to the rotating body side; a pressure adjustment space provided between the stationary body and a high-pressure-side end surface of the sealing member; and a communication passage having one end communicating with the low-pressure side and the other end communicating with the pressure adjustment space.Type: ApplicationFiled: January 31, 2023Publication date: August 17, 2023Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Takashi Mitsumata, Kohei Ozaki, Azumi Yoshida, Masaya Kawano
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Publication number: 20220316523Abstract: A fluid film bearing includes a plurality of bearing pads that are arranged in a circumferential direction of a rotating body that rotates about an axis, and that support the rotating body via a fluid film, wherein the bearing pad includes a base layer made of metal, an elastic layer that is layered on the rotating body side of the base layer, and that is made of an elastically deformable elastic material, a sliding layer that is layered on the rotating body side of the elastic layer, and that opposes the rotating body and is made of a bearing material, and a metal plate that is layered between the elastic layer and the sliding layer, and that is more rigid than the elastic layer and the sliding layer.Type: ApplicationFiled: March 15, 2022Publication date: October 6, 2022Inventors: Yoshitomo NODA, Takuzo SHIGIHARA, Shimpei YOKOYAMA, Chihiro YOSHIMINE, Masaya KAWANO
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Publication number: 20220107228Abstract: A temperature measuring device includes an ultrasonic sensor attached to a rear surface side of the structural body having the multilayer structure, an acquisition unit configured to, through the ultrasonic sensor, acquire a signal of a reflected wave of an ultrasonic wave incident at the internal side of the structural body, an extraction unit configured to extract, from the signal of the reflected wave, a domain including a reflected wave reflected on a surface on the internal side of the structural body, and an identification unit configured to, based on a signal of the reflected wave in the extracted domain, identify the temperature of the surface on the internal side of the structural body.Type: ApplicationFiled: June 21, 2021Publication date: April 7, 2022Inventors: Masaya KAWANO, Masahiro SUGIHARA, Tadashi KIMURA, Shinsuke SATO
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Patent number: 10879227Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: GrantFiled: December 10, 2019Date of Patent: December 29, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
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Patent number: 10720339Abstract: A fan-out wafer-level packaging method and the package produced thereof are provided in the present application.Type: GrantFiled: April 27, 2017Date of Patent: July 21, 2020Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Masaya Kawano, Ka Fai Chang
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Publication number: 20200118994Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: ApplicationFiled: December 10, 2019Publication date: April 16, 2020Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
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Patent number: 10580763Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: GrantFiled: January 3, 2019Date of Patent: March 3, 2020Assignee: Renesas Electronics CorporationInventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
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Publication number: 20190393051Abstract: A fan-out wafer-level packaging method and the package produced thereof are provided in the present application.Type: ApplicationFiled: April 27, 2017Publication date: December 26, 2019Inventors: Masaya KAWANO, Ka Fai Chang
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Publication number: 20190139953Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: ApplicationFiled: January 3, 2019Publication date: May 9, 2019Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
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Patent number: 10224318Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: GrantFiled: September 25, 2017Date of Patent: March 5, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
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Patent number: 9978512Abstract: A circuit device, includes a semiconductor substrate, and a first inductor provided over said semiconductor substrate, and a first interconnect provided over said semiconductor substrate and coupled with first inductor.Type: GrantFiled: November 9, 2016Date of Patent: May 22, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masaya Kawano, Yasutaka Nakashiba
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Publication number: 20180019237Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: ApplicationFiled: September 25, 2017Publication date: January 18, 2018Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
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Patent number: 9847325Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: GrantFiled: November 17, 2016Date of Patent: December 19, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
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Publication number: 20170236810Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: ApplicationFiled: November 17, 2016Publication date: August 17, 2017Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
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Publication number: 20170053738Abstract: A circuit device, includes a semiconductor substrate, and a first inductor provided over said semiconductor substrate, and a first interconnect provided over said semiconductor substrate and coupled with first inductor.Type: ApplicationFiled: November 9, 2016Publication date: February 23, 2017Inventors: Masaya KAWANO, Yasutaka NAKASHIBA
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Patent number: 9524953Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: GrantFiled: June 24, 2016Date of Patent: December 20, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
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Patent number: 9502175Abstract: A circuit device includes a semiconductor substrate, a first inductor provided over the semiconductor substrate, and a second inductor provided over the semiconductor substrate and coupled to the first inductor. The first inductor and second inductor are wound in a same direction with each other from respective inner end portions to respective outer end portions thereof.Type: GrantFiled: July 23, 2014Date of Patent: November 22, 2016Assignee: Renesas Electronics CorporationInventors: Masaya Kawano, Yasutaka Nakashiba