Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: A circuit device includes a semiconductor substrate, a first inductor provided over the semiconductor substrate, and a second inductor provided over the semiconductor substrate and coupled to the first inductor. The first inductor and second inductor are wound in a same direction with each other from respective inner end portions to respective outer end portions thereof.

Abstract: The device includes a first inductor, a first insulating layer, a second inductor, and a third inductor. The first inductor includes a helical conductive pattern. The second inductor is located in a region overlapping the first inductor through the first insulating layer. The second inductor includes a helical conductive pattern. The third inductor is connected in series to the second inductor, and includes a helical conductive pattern.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: A wind turbine blade used in a wind power generator that receives wind and rotates a rotating shaft of a generator includes at least two layers on a surface of a blade body, one of the layers being colored with a coating material different in color from the blade body and the rest of the layers. The layers are provided at least on a tip, particularly at a front edge of the wind turbine blade. A wind turbine blade monitoring system that monitors the wind turbine blade includes: an imaging unit that images the wind turbine blade in a predetermined position over a predetermined period at timing when the wind turbine blade passes through the predetermined position; and an indication unit that chronologically indicates imaging results of the wind turbine blade imaged by the imaging means.

Abstract: A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.

Abstract: A semiconductor device including a metal frame having a penetrating opening; a semiconductor chip provided in the opening; an insulating layer provided on the upper surface of the metal frame such that the insulating layer covers the upper surface, which is the circuit-formed surface of the semiconductor chip; an interconnect layer provided only on the upper-surface side of the metal frame with intervention of the insulating material and electrically connected to a circuit of the semiconductor chip; a via conductor provided on the upper surface of said semiconductor chip to electrically connect the circuit of the semiconductor chip and the interconnect layer; and a resin layer provided on the lower surface of the metal frame.

Abstract: A semiconductor package has: a first chip; and a second chip. The first chip has: an insulating resin layer formed on a principal surface of the first chip; a bump-shaped first internal electrode group that is so formed in a region of the insulating resin layer as to penetrate through the insulating resin layer and is electrically connected to the second chip; an external electrode group used for electrical connection to an external device; and an electrostatic discharge protection element group electrically connected to the external electrode group. The first internal electrode group is not electrically connected to the electrostatic discharge protection element group.

Abstract: A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference of a side surface of the through electrode 129 and extending through the semiconductor substrate 101. In addition, the semiconductor device 100 also includes a protruding portion 146, being provided at least in the vicinity of a back surface of a device-forming surface of the semiconductor substrate 101 so as to contact with the through electrode 129, and protruding in a direction along the surface of the semiconductor substrate 101 toward an interior of the through electrode 129.

Abstract: A semiconductor device 1 has a semiconductor chip 10. The semiconductor chip 10 is constituted as having a semiconductor substrate 12 and an interlayer insulating film 14 on the semiconductor substrate 12. The semiconductor substrate 12 has a plurality of through electrodes 22 (first through electrodes) and a plurality of through electrodes 24 (second through electrodes) formed therein. On the top surface S1 (first surface) of the semiconductor chip 10, there are provided connection terminals 32 (first connection terminals) and connection terminals 34 (second connection terminals). The connection terminals 32, 34 are connected to the through electrodes 22, 24, respectively. The connection terminals 32 herein are disposed at positions overlapping the through electrodes 22 in a plan view. On the other hand, the connection terminals 34 are disposed at positions not overlapping the through electrodes 24 in a plan view.

Abstract: A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.