Patents by Inventor Masaya Shima
Masaya Shima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804471Abstract: A method for manufacturing a semiconductor device is provided. The manufacturing method includes attaching a substrate to a sheet. The manufacturing method includes fragmenting the substrate into a plurality of individual chips. The manufacturing method includes expanding the sheet to widen the spacing between the plurality of chips. The manufacturing method includes covering the main surface and side surface of each of the plurality of chips with resin and sealing the chips to form a sealed body. The manufacturing method includes forming a stacked body in which a plurality of sealed bodies are stacked. The plurality of sealed bodies include a first sealed body and a second sealed body. Forming the stacked body includes stacking the second sealed body on the first sealed body in a state where the position of the chip in the second sealed body is offset in a direction in the plane with respect to the position of the chip in the first sealed body.Type: GrantFiled: March 1, 2021Date of Patent: October 31, 2023Assignee: KIOXIA CORPORATIONInventor: Masaya Shima
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Publication number: 20220293476Abstract: According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes inspecting each of plural chip regions of a substrate and determining the inspected chip region as a non-defective chip region or a defective chip region, the substrate including the plural chip regions formed as one system, the plural chip regions arranged in a planar direction on the substrate. The method includes forming a wiring, the wiring being connected to an electrode of the non-defective chip region among the plural chip regions, the wiring being not connected to an electrode of the defective chip region among the plural chip regions.Type: ApplicationFiled: September 9, 2021Publication date: September 15, 2022Applicant: Kioxia CorporationInventor: Masaya SHIMA
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Publication number: 20220084985Abstract: A method for manufacturing a semiconductor device is provided. The manufacturing method includes attaching a substrate to a sheet. The manufacturing method includes fragmenting the substrate into a plurality of individual chips. The manufacturing method includes expanding the sheet to widen the spacing between the plurality of chips. The manufacturing method includes covering the main surface and side surface of each of the plurality of chips with resin and sealing the chips to form a sealed body. The manufacturing method includes forming a stacked body in which a plurality of sealed bodies are stacked. The plurality of sealed bodies include a first sealed body and a second sealed body. Forming the stacked body includes stacking the second sealed body on the first sealed body in a state where the position of the chip in the second sealed body is offset in a direction in the plane with respect to the position of the chip in the first sealed body.Type: ApplicationFiled: March 1, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventor: Masaya SHIMA
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Patent number: 11107788Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: forming a semiconductor feature on a first surface of a substrate; forming a first insulating film on the semiconductor feature; forming a first wiring layer on the first insulating film; forming a second insulating film on the first wiring layer; forming a second wiring layer on the second insulating film; forming a first electrode on the second wiring layer; providing a protective adhesive that covers the first electrode and the second wiring layer; bonding a supporting substrate onto the protective adhesive; polishing a second surface of the substrate opposite to the first surface; removing the supporting substrate from the protective adhesive; and removing at least a portion of the protective adhesive to expose the first electrode.Type: GrantFiled: August 28, 2019Date of Patent: August 31, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Masaya Shima
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Patent number: 10804152Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.Type: GrantFiled: February 11, 2019Date of Patent: October 13, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaya Shima, Ippei Kume, Eiichi Shin, Eiji Takano, Takashi Shirono, Mika Fujii
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Publication number: 20200258858Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: forming a semiconductor feature on a first surface of a substrate; forming a first insulating film on the semiconductor feature; forming a first wiring layer on the first insulating film; forming a second insulating film on the first wiring layer; forming a second wiring layer on the second insulating film; forming a first electrode on the second wiring layer; providing a protective adhesive that covers the first electrode and the second wiring layer; bonding a supporting substrate onto the protective adhesive; polishing a second surface of the substrate opposite to the first surface; removing the supporting substrate from the protective adhesive; and removing at least a portion of the protective adhesive to expose the first electrode.Type: ApplicationFiled: August 28, 2019Publication date: August 13, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Masaya SHIMA
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Patent number: 10741505Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.Type: GrantFiled: January 7, 2019Date of Patent: August 11, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaya Shima, Eiji Takano, Ippei Kume, Yuki Noda
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Patent number: 10546769Abstract: According to one embodiment, a semiconductor manufacturing method for a stacked body that includes a semiconductor substrate, a supporting substrate containing silicon, and a joining layer arranged between the semiconductor substrate and the supporting substrate to joint the semiconductor substrate and the supporting substrate, in which a surface of the semiconductor substrate opposite to the joining layer is to be ground, includes irradiating the stacked body with electromagnetic wave having energy of 0.11 to 0.14 eV from a side of the supporting substrate, and separating the semiconductor substrate from the supporting substrate.Type: GrantFiled: March 3, 2016Date of Patent: January 28, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsuhiko Shirakawa, Kenji Takahashi, Eiji Takano, Masaya Shima
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Publication number: 20190348324Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.Type: ApplicationFiled: February 11, 2019Publication date: November 14, 2019Applicant: Toshiba Memory CorporationInventors: Masaya SHIMA, Ippei KUME, Eiichi SHIN, Eiji TAKANO, Takashi SHIRONO, Mika FUJII
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Patent number: 10475675Abstract: An apparatus for manufacturing a semiconductor device includes a stage configured to hold tape adhering to a second surface of a semiconductor wafer having the second surface and a first surface opposite to the second surface, a vacuum mechanism attachable to an upper side of a substrate provided to adhere to the first surface, a driving unit configured to drive the vacuum mechanism in a direction by which the vacuum mechanism is separated from the substrate, and a cooling unit configured to cool the tape.Type: GrantFiled: April 20, 2016Date of Patent: November 12, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Jun Tanaka, Masaya Shima
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Publication number: 20190139908Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.Type: ApplicationFiled: January 7, 2019Publication date: May 9, 2019Inventors: Masaya SHIMA, Eiji TAKANO, Ippei KUME, Yuki NODA
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Patent number: 10211165Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.Type: GrantFiled: September 4, 2017Date of Patent: February 19, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaya Shima, Eiji Takano, Ippei Kume, Yuki Noda
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Patent number: 10199253Abstract: A method of manufacturing a semiconductor device includes disposing a peel-off layer on the second surface of the first substrate, wherein the second surface of the first substrate comprises semiconductor integrated circuits, and the peel-off layer does not extend to an outer peripheral portion of the first substrate, bonding a second substrate to the peel-off layer via a bonding layer, attaching a tape onto the first surface of the first substrate, wherein the tape comprises an adhesive agent having an adhesive strength capable of being lowered by UV irradiation, irradiating a portion of the adhesive agent provided at the outer peripheral portion with UV rays directed toward the first surface, and separating the first substrate from the second substrate at the adhesive agent portion and the peel-off layer portion.Type: GrantFiled: March 2, 2015Date of Patent: February 5, 2019Assignee: Toshiba Memory CorporationInventors: Masaya Shima, Kenji Takahashi
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Publication number: 20180277493Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.Type: ApplicationFiled: September 4, 2017Publication date: September 27, 2018Inventors: Masaya SHIMA, Eiji TAKANO, Ippei KUME, Yuki NODA
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Patent number: 9646908Abstract: In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching.Type: GrantFiled: July 22, 2016Date of Patent: May 9, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Soichi Homma, Masaya Shima, Yuusuke Takano, Takeshi Watanabe, Katsunori Shibuya
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Publication number: 20170025321Abstract: In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching.Type: ApplicationFiled: July 22, 2016Publication date: January 26, 2017Inventors: Soichi HOMMA, Masaya SHIMA, Yuusuke TAKANO, Takeshi WATANABE, Katsunori SHIBUYA
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Publication number: 20160314998Abstract: An apparatus for manufacturing a semiconductor device includes a stage configured to hold tape adhering to a second surface of a semiconductor wafer having the second surface and a first surface opposite to the second surface, a vacuum mechanism attachable to an upper side of a substrate provided to adhere to the first surface, a driving unit configured to drive the vacuum mechanism in a direction by which the vacuum mechanism is separated from the substrate, and a cooling unit configured to cool the tape.Type: ApplicationFiled: April 20, 2016Publication date: October 27, 2016Inventors: Jun TANAKA, Masaya SHIMA
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Publication number: 20160276200Abstract: According to one embodiment, a semiconductor manufacturing method for a stacked body that includes a semiconductor substrate, a supporting substrate containing silicon, and a joining layer arranged between the semiconductor substrate and the supporting substrate to joint the semiconductor substrate and the supporting substrate, in which a surface of the semiconductor substrate opposite to the joining layer is to be ground, includes irradiating the stacked body with electromagnetic wave having energy of 0.11 to 0.14 eV from a side of the supporting substrate, and separating the semiconductor substrate from the supporting substrate.Type: ApplicationFiled: March 3, 2016Publication date: September 22, 2016Inventors: Tatsuhiko SHIRAKAWA, Kenji TAKAHASHI, Eiji TAKANO, Masaya SHIMA
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Publication number: 20160079109Abstract: A method of manufacturing a semiconductor device includes disposing a peel-off layer on the second surface of the first substrate, wherein the second surface of the first substrate comprises semiconductor integrated circuits, and the peel-off layer does not extend to an outer peripheral portion of the first substrate, bonding a second substrate to the peel-off layer via a bonding layer, attaching a tape onto the first surface of the first substrate, wherein the tape comprises an adhesive agent having an adhesive strength capable of being lowered by UV irradiation, irradiating a portion of the adhesive agent provided at the outer peripheral portion with UV rays directed toward the first surface, and separating the first substrate from the second substrate at the adhesive agent portion and the peel-off layer portion.Type: ApplicationFiled: March 2, 2015Publication date: March 17, 2016Inventors: Masaya SHIMA, Kenji TAKAHASHI
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Patent number: 9190373Abstract: According to one embodiment, a semiconductor substrate, a redistribution trace, and a surface layer are provided, with the surface layer provided on the redistribution trace. On the semiconductor substrate, a wire and a pad electrode are formed. The redistribution trace is formed on the semiconductor substrate. The surface layer is larger in width than the redistribution trace, and extends beyond the edge of the redistribution trace.Type: GrantFiled: August 31, 2011Date of Patent: November 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Migita, Hirokazu Ezawa, Soichi Yamashita, Masaya Shima