Patents by Inventor Masaya Ueno

Masaya Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916112
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as a device surface, a second main surface at a side opposite to the first main surface, and a side surface connecting the first main surface and the second main surface, a main surface insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface continuous to the side surface of the SiC semiconductor layer, and a boundary modified layer including a first region that is modified to be of a property differing from the SiC monocrystal and a second region that is modified to be of a property differing from the insulating material, and being formed across the side surface of the SiC semiconductor layer and the insulating side surface of the main surface insulating layer.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 27, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Yasuhiro Kawakami, Yuki Nakano, Masaya Ueno, Seiya Nakazawa, Sawa Haruyama, Yasunori Kutsuma
  • Publication number: 20230290887
    Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, a semiconductor layer formed on the principal surface of the semiconductor substrate, the semiconductor layer including a first-conductivity-type low concentration layer in contact with the principal surface of the semiconductor substrate and a first-conductivity-type high concentration layer that is formed at a surface layer portion of a surface, which is on a side opposite to the principal surface, of the semiconductor layer and that has a higher impurity concentration than the low concentration layer, and a Schottky electrode that is formed on the surface of the semiconductor layer and that forms a Schottky junction portion between the high concentration layer and the Schottky electrode.
    Type: Application
    Filed: September 3, 2021
    Publication date: September 14, 2023
    Applicant: ROHM CO., LTD.
    Inventor: Masaya UENO
  • Publication number: 20230287893
    Abstract: A rotor, a magnetic bearing, and a drive unit that rotationally drives the rotor. The magnetic bearing includes a bearing stator and a ring-shaped bearing rotor member. The drive unit has a drive stator and a ring-shaped drive rotor member. The bearing stator has a plurality of bearing stator cores consisting of a magnetic material, disposed on an outer peripheral side of the bearing rotor member. The bearing stator core has a first portion extending in a first direction orthogonal to a direction facing the bearing rotor member, and a pair of second portions extending to a bearing rotor member side from both end portions in the first direction of the first portion. The drive stator is formed so as to pass through a position between an outer peripheral surface of the rotor and the first portion core and between the pair of second portions.
    Type: Application
    Filed: May 13, 2021
    Publication date: September 14, 2023
    Applicant: IWAKI CO., LTD.
    Inventors: Toshiki ONIDUKA, Shinichirou KOREEDA, Toshiaki KAMEI, Hikaru SAITOU, Masaya UENO, Takuya SEKI
  • Publication number: 20230223433
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.
    Type: Application
    Filed: February 22, 2023
    Publication date: July 13, 2023
    Inventors: Yuki NAKANO, Masaya UENO, Sawa HARUYAMA, Yasuhiro KAWAKAMI, Seiya NAKAZAWA, Yasunori KUTSUMA
  • Publication number: 20230223445
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.
    Type: Application
    Filed: March 8, 2023
    Publication date: July 13, 2023
    Inventors: Masaya UENO, Yuki NAKANO, Sawa HARUYAMA, Yasuhiro KAWAKAMI, Seiya NAKAZAWA, Yasunori KUTSUMA
  • Publication number: 20230187504
    Abstract: A SiC semiconductor device includes a SiC chip having a main surface that includes a first surface, a second surface hollowed in a thickness direction outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a trench structure formed at the first surface such as to be exposed from the connecting surface, and a sidewall wiring that is formed on the second surface such as to cover the connecting surface and that is electrically connected to the trench structure.
    Type: Application
    Filed: July 16, 2021
    Publication date: June 15, 2023
    Applicant: ROHM CO., LTD.
    Inventors: Kenji YAMAMOTO, Seigo MORI, Hiroaki SHIRAGA, Yuki NAKANO, Masaya UENO
  • Publication number: 20230187486
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventors: Minoru NAKAGAWA, Yuki NAKANO, Masatoshi AKETA, Masaya UENO, Seigo MORI, Kenji YAMAMOTO
  • Publication number: 20230170410
    Abstract: A SiC semiconductor device includes SiC chip having main surface that includes first surface, second surface hollowed in thickness direction at first depth outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a transistor structure formed at an inward portion of the first surface, the transistor structure including a trench gate structure that has a second depth less than the first depth and a trench source structure that has a third depth exceeding the second depth and that adjoins the trench gate structure in one direction, and a dummy structure formed at a peripheral edge portion of the first surface, the dummy structure including a plurality of dummy trench source structures which have the third depth and adjoin each other in the one direction.
    Type: Application
    Filed: July 16, 2021
    Publication date: June 1, 2023
    Applicant: ROHM CO., LTD.
    Inventors: Seigo MORI, Kenji YAMAMOTO, Hiroaki SHIRAGA, Yuki NAKANO, Masaya UENO
  • Patent number: 11626490
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: April 11, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Masaya Ueno, Yuki Nakano, Sawa Haruyama, Yasuhiro Kawakami, Seiya Nakazawa, Yasunori Kutsuma
  • Publication number: 20230103655
    Abstract: An electronic component includes a covered object, an electrode that covers the covered object and has an electrode side wall on the covered object, an inorganic insulating film that has an inner covering portion covering the electrode such as to expose the electrode side wall, and an organic insulating film that covers the electrode side wall.
    Type: Application
    Filed: May 12, 2021
    Publication date: April 6, 2023
    Applicant: ROHM CO., LTD.
    Inventors: Yuki NAKANO, Masaya UENO
  • Patent number: 11621319
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: April 4, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Masaya Ueno, Sawa Haruyama, Yasuhiro Kawakami, Seiya Nakazawa, Yasunori Kutsuma
  • Patent number: 11605707
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: March 14, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Minoru Nakagawa, Yuki Nakano, Masatoshi Aketa, Masaya Ueno, Seigo Mori, Kenji Yamamoto
  • Publication number: 20220320349
    Abstract: A semiconductor device includes: a semiconductor layer including a semiconductor substrate and an epitaxial layer of a first conductivity type formed on the semiconductor substrate; a surface electrode containing at least one selected from the group consisting of an aluminum alloy and aluminum and formed on the semiconductor layer; and an impurity region of a second conductivity type formed on a surface layer portion of the epitaxial layer and forming a pn junction with the epitaxial layer, wherein the surface electrode includes a Schottky portion that is in contact with a surface of the semiconductor layer and forms a Schottky junction with the epitaxial layer.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 6, 2022
    Inventors: Masaya UENO, Sawa HARUYAMA, Masaya SAITO
  • Publication number: 20210305363
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.
    Type: Application
    Filed: June 16, 2021
    Publication date: September 30, 2021
    Inventors: Minoru NAKAGAWA, Yuki NAKANO, Masatoshi AKETA, Masaya UENO, Seigo MORI, Kenji YAMAMOTO
  • Publication number: 20210296448
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as a device surface, a second main surface at a side opposite to the first main surface, and a side surface connecting the first main surface and the second main surface, a main surface insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface continuous to the side surface of the SiC semiconductor layer, and a boundary modified layer including a first region that is modified to be of a property differing from the SiC monocrystal and a second region that is modified to be of a property differing from the insulating material, and being formed across the side surface of the SiC semiconductor layer and the insulating side surface of the main surface insulating layer.
    Type: Application
    Filed: August 8, 2019
    Publication date: September 23, 2021
    Inventors: Yasuhiro KAWAKAMI, Yuki NAKANO, Masaya UENO, Seiya NAKAZAWA, Sawa HARUYAMA, Yasunori KUTSUMA
  • Publication number: 20210234007
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.
    Type: Application
    Filed: August 8, 2019
    Publication date: July 29, 2021
    Inventors: Masaya UENO, Yuki NAKANO, Sawa HARUYAMA, Yasuhiro KAWAKAMI, Seiya NAKAZAWA, Yasunori KUTSUMA
  • Publication number: 20210233994
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.
    Type: Application
    Filed: August 8, 2019
    Publication date: July 29, 2021
    Inventors: Yuki NAKANO, Masaya UENO, Sawa HARUYAMA, Yasuhiro KAWAKAMI, Seiya NAKAZAWA, Yasunori KUTSUMA
  • Patent number: 11069771
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 20, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Minoru Nakagawa, Yuki Nakano, Masatoshi Aketa, Masaya Ueno, Seigo Mori, Kenji Yamamoto
  • Publication number: 20200243641
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.
    Type: Application
    Filed: May 17, 2018
    Publication date: July 30, 2020
    Inventors: Minoru NAKAGAWA, Yuki NAKANO, Masatoshi AKETA, Masaya UENO, Seigo MORI, Kenji YAMAMOTO
  • Patent number: 10501710
    Abstract: A cleaner composition consisting essentially of (A) 90.0-99.9 wt % of an organic solvent and (B) 0.1-10.0 wt % of a C3-C6 alcohol, and containing (C) 20-300 ppm of sodium and/or potassium is effective for cleaning a surface of a silicon semiconductor substrate. A satisfactory degree of cleanness is achieved within a short time and at a high efficiency without causing corrosion to the substrate.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 10, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Masaya Ueno, Hideyoshi Yanagisawa