Abstract: The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. Apparatus for preventing execution of a transaction such as storage access from obstruction by bus competition with low-speed IO access. The invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion unit for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage for storing access data up to a predetermined amount when the access destination is a predetermined module.

Abstract: An information processing apparatus includes a volatile storage unit and a nonvolatile storage device for storing at least algorithm information for processings executed by the processing unit, processed data inclusive of display-destined data generated in the storage unit and circuit state information concerning individual circuits incorporated in the information processing apparatus during operation of the information processing apparatus, and a control unit for setting a predetermined operation-mode state in accordance with predetermined rules of state transition so as to store selectively the algorithm information, the processed data and the circuit state information in the volatile storage unit and nonvolatile storage device in dependence on the conditions imposed externally through manipulation of the apparatus, whereby the time required for activating or resuming the information processing apparatus is reduced.

Abstract: The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency.

Abstract: An information processing apparatus includes a volatile storage unit and a nonvolatile storage device for storing at least algorithm information for processings executed by the processing unit, processed data inclusive of display-destined data generated in the storage unit and circuit state information concerning individual circuits incorporated in the information processing apparatus during operation of the information processing apparatus, and a control unit for setting a predetermined operation-mode state in accordance with predetermined rules of state transition so as to store selectively the algorithm information, the processed data and the circuit state information in the volatile storage unit and nonvolatile storage device in dependence on the conditions imposed externally through manipulation of the apparatus, whereby the time required for activating or resuming the information processing apparatus is reduced.

Abstract: An information processing apparatus includes a volatile storage unit and a nonvolatile storage device for storing at least algorithm information for processings executed by the processing unit, processed data inclusive of display-destined data generated in the storage unit and circuit state information concerning individual circuits incorporated in the information processing apparatus during operation of the information processing apparatus, and a control unit for setting a predetermined operation-mode state in accordance with predetermined rules of state transition so as to store selectively the algorithm information, the processed data and the circuit state information in the volatile storage unit and nonvolatile storage device in dependence on the conditions imposed externally through manipulation of the apparatus, whereby the time required for activating or resuming the information processing apparatus is reduced.

Abstract: The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. The present invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion means for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage means for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to give a bus occupation right to the bus master.

Abstract: A system for providing a service through a non-contact communication unit such as a wireless communication unit is disclosed. Specifically, an electronic ticket is communicated between a so-called mobile terminal and the non-contact communication unit equipped in a ticket examiner. The ticket examiner comprises a stocker for storing magnetized slips, roll paper or plastic slips, and a shaper for cutting the magnetized slip or the roll paper into a proper size. The ticket examiner confirms the validity of the electronic ticket for issuing a ticket.

Abstract: There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.

Abstract: A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit and each including at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit provided internally of the node. The system further includes a transfer end signal indicating an end of the data transfer, in synchronism with the clock signal, and a phase reference signal bus connected to each of the plural nodes, a data bus connected to each of the plural nodes for transmitting the data and a transfer end signal bus connected to each of the plural nodes for transmitting the transfer end signal.

Abstract: A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.

Abstract: An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.

Abstract: A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit. Each node includes at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit in response to the phase reference signal, and a transfer end signal indicating an end of transferring the data, respectively, in synchronism with the clock signal. A phase reference signal bus is connected to each node. A data bus is connected to each node for transmitting the data and a transfer end signal bus is connected to each node for transmitting the transfer end signal. A sender node includes a sending unit for sending data to a receiver node with a delay after the phase reference signal transmitted to the phase reference signal bus by the sender node, and sending simultaneously the transfer end signal to the receiver node.

Abstract: In a connector having a plurality of first contact groups arranged in a predetermined pattern, conductors whose one ends are connected to the first contact groups, and a plurality of second contact groups arranged in a pattern corresponding to the pattern of the first contact groups, the conductors for connecting the first contact groups and the second contact groups cause portions of the first contact groups to be connected to the second contact groups at different positions within the above-described pattern. Accordingly, even when the contacts of the same sort of signal lines having one-to-one correspondence are allocated to the contact conductors located at the same positions within the boards for constituting the respective modules, the one-to-one correspondence can be maintained, and thus the printed-circuit boards of the modules can be commonly utilized.