Patents by Inventor Masayoshi Fuchi

Masayoshi Fuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149082
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 12, 2022
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Masayoshi FUCHI
  • Patent number: 11271020
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: March 8, 2022
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Masayoshi Fuchi
  • Publication number: 20210013235
    Abstract: A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Applicant: Japan Display Inc.
    Inventors: Tatsuya TODA, Toshinari SASAKI, Masayoshi FUCHI
  • Publication number: 20200321359
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Application
    Filed: June 19, 2020
    Publication date: October 8, 2020
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Masayoshi Fuchi
  • Patent number: 10707242
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 7, 2020
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Masayoshi Fuchi
  • Patent number: 10396187
    Abstract: A semiconductor device including a first oxide insulating layer, a barrier layer above the first oxide insulating layer, the barrier layer including an opening, a second oxide insulating layer above the first oxide insulating layer at a position overlapping the opening, an oxide semiconductor layer facing the first oxide insulating layer interposed by the second oxide insulating layer at a position overlapping the opening, a gate electrode facing the oxide semiconductor layer at side opposite to the first oxide insulating layer with respect to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. A contained amount of oxygen in the first oxide insulating layer is larger than a contained amount of oxygen in the second oxide insulating layer.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: August 27, 2019
    Assignee: Japan Display Inc.
    Inventors: Toshinari Sasaki, Masahiro Watabe, Masayoshi Fuchi, Isao Suzumura, Marina Shiokawa
  • Patent number: 10374096
    Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: August 6, 2019
    Assignee: Japan Display Inc.
    Inventors: Miyuki Ishikawa, Arichika Ishida, Masayoshi Fuchi, Hajime Watakabe, Takashi Okada
  • Patent number: 10276601
    Abstract: According to one embodiment, a display device includes an insulating substrate, a first transistor including a first semiconductor layer of silicon and a first electrode, a first insulating layer provided above the first semiconductor layer, a second transistor including a second semiconductor layer of an oxide semiconductor, a second electrode and a conductive layer electrically connected to the second semiconductor layer, and a second insulating layer provided above the first insulating layer and the second semiconductor layer, the first electrode being electrically connected to the first semiconductor layer in a first hole, and the second electrode being in contact with the conductive layer in a second hole.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 30, 2019
    Assignee: Japan Display Inc.
    Inventors: Noriyoshi Kanda, Arichika Ishida, Masayoshi Fuchi
  • Publication number: 20190096915
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 28, 2019
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Masayoshi FUCHI
  • Patent number: 10177174
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 8, 2019
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Masayoshi Fuchi
  • Publication number: 20180226498
    Abstract: A semiconductor device including a first oxide insulating layer, a barrier layer above the first oxide insulating layer, the barrier layer including an opening, a second oxide insulating layer above the first oxide insulating layer at a position overlapping the opening, an oxide semiconductor layer facing the first oxide insulating layer interposed by the second oxide insulating layer at a position overlapping the opening, a gate electrode facing the oxide semiconductor layer at side opposite to the first oxide insulating layer with respect to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. A contained amount of oxygen in the first oxide insulating layer is larger than a contained amount of oxygen in the second oxide insulating layer.
    Type: Application
    Filed: January 26, 2018
    Publication date: August 9, 2018
    Inventors: Toshinari SASAKI, Masahiro Watabe, Masayoshi Fuchi, Isao Suzumura, Marina Shiokawa
  • Patent number: 9911859
    Abstract: According to one embodiment, a thin-film transistor and a method of manufacturing the same achieve size reduction of the thin-film transistor while using an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. A gate electrode is arranged at a position spaced from the channel region of the oxide semiconductor layer so as to face the channel region. A source electrode is electrically connected to the source region of the oxide semiconductor layer. A drain electrode is electrically connected to the drain region of the oxide semiconductor layer. An undercoat layer adjoins the source region and the drain region of the oxide semiconductor layer. A hydrogen blocking layer has a hydrogen concentration lower than that in the undercoat layer and separates the undercoat layer and the channel region of the oxide semiconductor layer.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: March 6, 2018
    Assignee: Japan Display Inc.
    Inventors: Hajime Watakabe, Arichika Ishida, Takashi Okada, Masayoshi Fuchi, Akihiro Hanada
  • Publication number: 20180061857
    Abstract: According to one embodiment, a display device includes an insulating substrate, a first transistor including a first semiconductor layer of silicon and a first electrode, a first insulating layer provided above the first semiconductor layer, a second transistor including a second semiconductor layer of an oxide semiconductor, a second electrode and a conductive layer electrically connected to the second semiconductor layer, and a second insulating layer provided above the first insulating layer and the second semiconductor layer, the first electrode being electrically connected to the first semiconductor layer in a first hole, and the second electrode being in contact with the conductive layer in a second hole.
    Type: Application
    Filed: August 22, 2017
    Publication date: March 1, 2018
    Applicant: Japan Display Inc.
    Inventors: Noriyoshi KANDA, Arichika Ishida, Masayoshi Fuchi
  • Publication number: 20180013006
    Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Applicant: Japan Display Inc.
    Inventors: Miyuki ISHIKAWA, Arichika ISHIDA, Masayoshi FUCHI, Hajime WATAKABE, Takashi OKADA
  • Publication number: 20170358606
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 14, 2017
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Masayoshi FUCHI
  • Patent number: 9831349
    Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 28, 2017
    Assignee: Japan Display Inc.
    Inventors: Miyuki Ishikawa, Arichika Ishida, Masayoshi Fuchi, Hajime Watakabe, Takashi Okada
  • Patent number: 9780227
    Abstract: According to one embodiment, a thin-film transistor and a method of manufacturing the thin-film transistor provided herein achieve enhanced reliability by preventing a disconnection in a gate insulating film at a position corresponding to an end surface of an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. The channel region is placed between the source region and the drain region. The gate insulating film covers the oxide semiconductor layer in a range from at least a part of an upper surface to an end surface continuous with the upper surface of the oxide semiconductor layer. The oxide semiconductor layer is formed so as to have an oxygen concentration that becomes lower from a top side to a bottom side and the end surface is inclined so as to diverge from the top side to the bottom side.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: October 3, 2017
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Masayoshi Fuchi, Hajime Watakabe, Takashi Okada, Arichika Ishida
  • Publication number: 20170162715
    Abstract: According to one embodiment, a method of manufacturing a thin film transistor, includes forming an island-like first insulating layer containing oxygen above an insulating substrate, forming an oxide semiconductor layer above the insulating substrate and the first insulating layer and in contact with the first insulating layer, and performing heat treatment to supply oxygen from the first insulating layer to an overlapping area of the oxide semiconductor layer, which is overlaid on the first insulating layer.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 8, 2017
    Applicant: Japan Display Inc.
    Inventors: Takashi OKADA, Masayoshi FUCHI, Hajime WATAKABE, Akihiro HANADA
  • Patent number: 9647134
    Abstract: According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 9, 2017
    Assignee: JAPAN DISPLAY INC.
    Inventors: Masato Hiramatsu, Masayoshi Fuchi, Arichika Ishida
  • Publication number: 20160172503
    Abstract: According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film.
    Type: Application
    Filed: February 24, 2016
    Publication date: June 16, 2016
    Applicant: Japan Display Inc.
    Inventors: Masato HIRAMATSU, Masayoshi FUCHI, Arichika ISHIDA