Patents by Inventor Masayoshi Iwayama

Masayoshi Iwayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110180861
    Abstract: A magnetic random access memory includes the following structure. A first magnetoresistive effect element is formed on a semiconductor substrate. The first magnetoresistive effect element includes a first fixed layer, a first nonmagnetic layer and a first free layer. The first fixed layer has an invariable magnetization direction. The first nonmagnetic layer is formed on the first fixed layer. The first free layer is formed on the first nonmagnetic layer and has a variable magnetization direction. An active region is formed on the substrate. A first select transistor includes a first diffusion region and a second diffusion region which are formed in the active region. The first diffusion region is electrically connected to the first free layer. A second select transistor includes the first diffusion region and a third diffusion region which are formed in the active region. A first interconnect layer is electrically connected to the first fixed layer.
    Type: Application
    Filed: April 28, 2010
    Publication date: July 28, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masayoshi IWAYAMA
  • Patent number: 7919826
    Abstract: A magnetoresistive element includes a first stacked structure formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed and a first nonmagnetic layer, a second stacked structure formed on the first stacked structure by sequentially stacking a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, and a circumferential wall formed in contact with a circumferential surface of the second stacked structure to surround the second stacked structure, and made of an insulator. A circumferential surface of the first stacked structure is substantially perpendicular. The second stacked structure has a tapered shape which narrows upward.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: April 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayoshi Iwayama, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani
  • Publication number: 20110062417
    Abstract: First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion on a channel region between the source/drain regions. Third semiconductor layers are on the first portions of the second semiconductor layer. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. Contact plugs are in the first semiconductor layers, the first portions of the second semiconductor layers and the third semiconductor layers in the source/drain regions. A diameter of the contact plug in the second semiconductor layer is smaller than a diameter of the contact plug in the first and third semiconductor layers.
    Type: Application
    Filed: February 4, 2010
    Publication date: March 17, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayoshi Iwayama, Takeshi Kajiyama, Yoshiaki Asao
  • Publication number: 20110062421
    Abstract: First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion in a linear form in a channel region between the source/drain regions. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. A film thickness of the second portion of the second semiconductor layer is smaller than a film thickness of the first portion of the second semiconductor layer.
    Type: Application
    Filed: February 4, 2010
    Publication date: March 17, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayoshi Iwayama, Yoshiaki Asao, Takeshi Kajiyama
  • Publication number: 20100200900
    Abstract: A magnetoresistive element of an aspect of the present invention including a lower electrode provided on an insulating layer on a semiconductor substrate, a first ferromagnetic layer provided on the lower electrode, a first tunnel barrier layer provided on the first ferromagnetic layer, a second ferromagnetic layer provided on the first tunnel barrier layer, and an upper electrode provided on the second ferromagnetic layer, wherein the upper electrode has a hexagonal cross-sectional shape, and a maximum size of the upper electrode in a first direction is larger than a size of the first tunnel barrier layer in the first direction, the first direction being horizontal relative to a surface of the semiconductor substrate.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 12, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masayoshi Iwayama
  • Publication number: 20100197044
    Abstract: A magnetic material of a magnetoresistive element is formed on a lower electrode. An upper electrode is formed on the magnetic material. A resist for nano-imprint lithography is formed on the upper electrode. A first pattern or a second pattern is formed in the resist by setting a first template or a second template into contact with the resist and curing the resist. The first template has the first pattern that corresponds to the magnetoresistive element and the lower electrode. The second template has the second pattern that corresponds to the magnetoresistive element and the upper electrode. The magnetic material and the lower electrode are patterned at the same time by using the resist having the first pattern, or the magnetic material and the upper electrode are patterned at the same time by using the resist having the second pattern.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 5, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi KAJIYAMA, Yoshiaki ASAO, Minoru AMANO, Shigeki TAKAHASHI, Masayoshi IWAYAMA, Kuniaki SUGIURA
  • Patent number: 7727778
    Abstract: A magnetoresistive element includes a stack formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed, a first nonmagnetic layer, a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, a first circumferential wall provided on the second nonmagnetic layer in contact with a circumferential surface of the second fixed layer to surround the second fixed layer, and made of an insulator, and a second circumferential wall provided on the first nonmagnetic layer in contact with a circumferential surface of the free layer to surround the free layer, and made of an insulator.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayoshi Iwayama, Keiji Hosotani, Takeshi Kajiyama, Yoshiaki Asao
  • Publication number: 20100053823
    Abstract: A magnetoresistive element includes a stack formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed, a first nonmagnetic layer, a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, a first circumferential wall provided on the second nonmagnetic layer in contact with a circumferential surface of the second fixed layer to surround the second fixed layer, and made of an insulator, and a second circumferential wall provided on the first nonmagnetic layer in contact with a circumferential surface of the free layer to surround the free layer, and made of an insulator.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 4, 2010
    Inventors: Masayoshi Iwayama, Keiji Hosotani, Takeshi Kajiyama, Yoshiaki Asao
  • Publication number: 20080277703
    Abstract: A magnetic random access memory includes a single tunnel junction element which includes a first fixed layer, a first recording layer, and a first nonmagnetic layer, a double tunnel junction element which includes a second fixed layer and a third fixed layer, a second recording layer, a second nonmagnetic layer formed between the second fixed layer and the second recording layer, and a third nonmagnetic layer formed between the third fixed layer and the second recording layer, and in which the magnetization directions in the second fixed layer and the second recording layer take one of the parallel state and the antiparallel state in accordance with a direction of an electric current flowing between the second fixed layer and the second recording layer, and a transistor connected to a memory cell having the single tunnel junction element and the double tunnel junction element connected in parallel.
    Type: Application
    Filed: April 23, 2008
    Publication date: November 13, 2008
    Inventor: Masayoshi Iwayama
  • Publication number: 20080265347
    Abstract: A magnetoresistive element includes a first stacked structure formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed and a first nonmagnetic layer, a second stacked structure formed on the first stacked structure by sequentially stacking a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, and a circumferential wall formed in contact with a circumferential surface of the second stacked structure to surround the second stacked structure, and made of an insulator. A circumferential surface of the first stacked structure is substantially perpendicular. The second stacked structure has a tapered shape which narrows upward.
    Type: Application
    Filed: April 23, 2008
    Publication date: October 30, 2008
    Inventors: Masayoshi Iwayama, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani
  • Publication number: 20080224117
    Abstract: A semiconductor memory device includes a first resistance change element having a first portion and a second portion, the first portion and the second portion having a first space in a first direction, and a second resistance change element formed to have a distance to the first resistance change element in the first direction, and having a third portion and a fourth portion, the third portion and the fourth portion having a second space in the first direction, and the first space and the second space being shorter than the distance.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 18, 2008
    Inventor: Masayoshi IWAYAMA