Abstract: An image forming apparatus includes a mounting surface provided on a main body and on which paper is placed; a person detection section provided in the main body; a processor configured to control return from a sleep state of the main body, based on the detection of a person by the person detection section, and perform control such that in a case where there is no paper on the mounting surface when transition to the sleep state, a nearby person approaching the main body is included in a detection target of the person detection section, and a passerby passing near the main body is not included in the detection target, in the sleep state, and in a case where there is a paper on the mounting surface when the transition, the nearby person and the passerby are included in the detection target, in the sleep state; and a notification section that notifies of paper remaining in a case where there is a paper on the mounting surface after the return.

Abstract: According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.

Abstract: Provided are a program, an information processing device, a method, and a system that allow properties of an organized party to be easily grasped. An information processing device 10 is an information processing device for executing a game and includes: a setting unit 231 for setting two or more game media on a deck with which indicator information is associated; an indicator-information-point calculation unit 232 for determining points for each item of the indicator information on the basis of predetermined data associated with the game media; and an indicator-information determination unit 233 for determining the indicator information to be displayed on a game screen on the basis of the points for each item of the indicator information obtained by the indicator-information-point calculation unit 232 and associating the determined indicator information with the deck.

Abstract: There is provided a novel ingredient that exhibits an exceptional effect for enhancing muscle using a fatty acid. A composition for muscle enhancement, characterized in that the composition contains, as an active component, at least one selected from the group consisting of C13, C14, or C15 fatty acids and fatty acid esters that include these fatty acids. The fatty acid is preferably at least one selected from tridecanoic acid, tetradecanoic acid, or pentadecanoic acid. The composition for muscle enhancement is suitably used in the form of, inter alia, an oil and fat composition, a food or beverage, a supplement, or an animal feed.

Abstract: A sensor module includes: a count unit configured to generate first to n-th count values of a time event of one of a measurement target signal output from a physical quantity sensor and a reference periodic signal output from a reference periodic signal generation unit in synchronization with the other; a time digital value generation unit configured to generate first to n-th time digital values based on a phase difference between the measurement target signal and the reference periodic signal; and a combined output value generation unit configured to generate an i-th combined output value based on the i-th time digital value and the i-th count value. A quantization error of the j-th combined output value is fed back to generation of the (j+1)-th combined output value, and a period of a change in the physical quantity when a frequency, at which the physical quantity changes, is a maximum frequency is longer than eight times an average period in which first to n-th combined output values are generated.

Abstract: According to one embodiment, a controller configured to manage second test information including status information indicating that a test related to a write operation and a read operation on a second storage area has not been executed. In response to receiving a command for acquiring information related to the second storage area from a host, the controller transmits the second test information to the host. When execution of the test on the second storage area is requested by the host, the controller executes the test related to the write operation and the read operation on the second storage area, and updates the status information of the second test information.

Abstract: An information processing system includes a host and a storage device that transmits a first pulse signal to the host and receives a second pulse signal from the host through a transmission line. The storage device has a first register to store a value of a first parameter and correction circuit to adjust a first duty ratio of the first pulse signal according to the value of the first parameter. The host includes a first calibration processor that measures a plurality of the first duty ratios as output from the storage device for different values of the first parameter to derive a first optimum value based on the measured first duty ratios and transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register.

Abstract: An information processing system includes a host and a storage device that transmits a first pulse signal to the host and receives a second pulse signal from the host through a transmission line. The storage device has a first register to store a value of a first parameter and correction circuit to adjust a first duty ratio of the first pulse signal according to the value of the first parameter. The host includes a first calibration processor that measures a plurality of the first duty ratios as output from the storage device for different values of the first parameter to derive a first optimum value based on the measured first duty ratios and transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register.

Abstract: An information processing system includes a host and a storage device that transmits a first pulse signal to the host and receives a second pulse signal from the host through a transmission line. The storage device has a first register to store a value of a first parameter and correction circuit to adjust a first duty ratio of the first pulse signal according to the value of the first parameter. The host includes a first calibration processor that measures a plurality of the first duty ratios as output from the storage device for different values of the first parameter to derive a first optimum value based on the measured first duty ratios and transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register.

Abstract: According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.

Abstract: The present invention relates to a medicament for treating and/or preventing inflammatory bowel disease, comprising a quinolone compound of the formula shown below as an active ingredient.

Abstract: According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.

Abstract: An information processing apparatus communicates with a storage device and includes a serial interface configured to support plural link rates, and a controller. The controller retrieves from the storage device via the serial interface information indicating a relationship between maximum power consumption and power consumption efficiency value for each link rate in a first power throttling mode that gives priority to performance and a second power throttling mode that gives priority to reduction of peak power, the power consumption efficiency value being a value that corresponds to the number of I/Os per watt, select the first or the second power throttling mode based on the retrieved information and a mode specified from one of three modes, and instruct the storage device to limit power consumption based on the selected power throttling mode.

Abstract: The present invention relates to a method for activating helper T cells, which includes the step of activating helper T cells by adding a WT1 peptide to antigen presenting cells, wherein the WT1 peptide has the ability to bind to any MHC class II molecule of an HLA-DRB1*0101 molecule, an HLA-DRB1*0401 molecule, an HLA-DRB1*0403 molecule, an HLA-DRB1*0406 molecule, an HLA-DRB1*0803 molecule, an HLA-DRB1*0901 molecule, an HLA-DRB1*1101 molecule, an HLA-DRB3*0202 molecule, an HLA-DRB4*0101 molecule, an HLA-DPB1*0201 molecule or an HLA-DPB1*0301 molecule, and the like.

Abstract: The present invention relates to a method for activating helper T cells, which includes the step of activating helper T cells by adding a WT1 peptide to antigen presenting cells, wherein the WT1 peptide has the ability to bind to any MHC class II molecule of an HLA-DRB1*0101 molecule, an HLA-DRB1*0401 molecule, an HLA-DRB1*0403 molecule, an HLA-DRB1*0406 molecule, an HLA-DRB1*0803 molecule, an HLA-DRB1*0901 molecule, an HLA-DRB1*1101 molecule, an HLA-DRB3*0202 molecule, an HLA-DRB4*0101 molecule, an HLA-DPB1*0201 molecule or an HLA-DPB1*0301 molecule, and the like.

Abstract: A storage device includes a receiving circuit including a correction circuit configured to correct an input signal from a host system based on correction factors and output the corrected input signal as an output signal containing a data value that is to be stored in the storage device, an interface controller configured to adjust the correction factors based on a difference value generated by the correction circuit using the output signal, and a transmission circuit configured to transmit the correction factors to the host system.

Abstract: One embodiment provides a switching regulator circuit having an overcurrent protection function that enables complete overcurrent protection though simple in configuration. The switching regulator circuit generates an output signal while boosting an input voltage by switching on/off a switching element using a PWM signal. The switching regulator circuit is equipped with a load switch which is connected to the switching element in series and is normally on. And, the switching regulator circuit is further equipped with an overcurrent protection circuit which keeps the load switch off if a current flowing through the switching element is an overcurrent.

Abstract: According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.

Abstract: An information processing apparatus communicates with a storage device and includes a serial interface configured to support plural link rates, and a controller. The controller retrieves from the storage device via the serial interface information indicating a relationship between maximum power consumption and power consumption efficiency value for each link rate in a first power throttling mode that gives priority to performance and a second power throttling mode that gives priority to reduction of peak power, the power consumption efficiency value being a value that corresponds to the number of I/Os per watt, select the first or the second power throttling mode based on the retrieved information and a mode specified from one of three modes, and instruct the storage device to limit power consumption based on the selected power throttling mode.

Abstract: According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.