Abstract: Disclosed is a controller which includes a CPU, a cache control unit, a tag control unit, a data unit, and a ROM. The cache control unit executes cache control operations for a process executed on the CPU, based on the process identifier in one of cache access modes: (A) cache nonuse, (B) cache use with block replacement permission, and (C) cache use with block replacement no-permission. The cache cannot be used when control information corresponding to a process identifier indicates (A), but can be used when control information indicates (B). When control information indicates (C), an instruction is sent from the cache to the CPU if a cache hit occurs, and from the ROM to the CPU if a cache miss occurs, but a block replacement is not executed.

Abstract: A microprocessor is provided with a self-diagnostic test function. The microprocessor comprises an input circuit for inputting at least a macro instruction and information necessary for self-diagnostic testing stored in an external memory; a decoder for decoding the inputted macro instruction; a micro instruction ROM for storing micro instructions; an incrementer for generating an incremented address by incrementing the address of the received address of the micro instruction ROM by 1. The microprocessor also includes an external test mode setting circuit (ETMSU) that inputs an incremented address and information necessary for self-diagnostic testing, and that outputs an incremented address when the microprocessor is operating in normal mode. In accordance with micro instructions outputted by the micro instruction ROM, the ETMSU outputs either an incremented address or information necessary for self-diagnostic testing when the microprocessor is operating in self-diagnostic testing mode.