Patents by Inventor Masayuki Imaizumi

Masayuki Imaizumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200137861
    Abstract: [Problem] To reduce deformation of a housing while reducing the risk of liquid penetration to the inside of a gantry. [Means for Solution] A housing 20 comprises a front cover 30, a main cover 40, a rear cover 50, and a scan window 60. The scan window 60 has a PC sheet 61, and elastic members 62 and 63. The front cover 30 has a receiving portion 32 in which the elastic member 62 is disposed, and a reinforcing portion 33 for reducing deformation of the PC sheet 61; the rear cover 50 has a receiving portion 52 in which the elastic member 63 is disposed, and a reinforcing portion 53 for reducing deformation of the PC sheet 61.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 30, 2020
    Inventors: Masayuki IMAIZUMI, Mitsuru KOBAYASHI, Kiyomi ABESHIMA
  • Patent number: 10510843
    Abstract: An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 17, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui, Naruhisa Miura, Yuji Abe, Masayuki Imaizumi
  • Publication number: 20190355821
    Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yukiyasu NAKAO, Masayuki IMAIZUMI, Shuhei NAKATA, Naruhisa MIURA
  • Patent number: 10418444
    Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: September 17, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
  • Publication number: 20190237558
    Abstract: A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.
    Type: Application
    Filed: April 3, 2019
    Publication date: August 1, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji HAMADA, Masayuki IMAIZUMI
  • Patent number: 10304939
    Abstract: A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: May 28, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Hamada, Masayuki Imaizumi
  • Patent number: 9985093
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 29, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro Kagawa, Akihiko Furukawa, Shiro Hino, Hiroshi Watanabe, Masayuki Imaizumi
  • Patent number: 9954072
    Abstract: A silicon-carbide semiconductor device that relaxes field intensity in a gate insulating film, and that has a low ON-resistance. The silicon-carbide semiconductor device includes: an n-type silicon-carbide substrate; a drift layer formed on a topside of the n-type silicon-carbide substrate; a trench formed in the drift layer and that includes therein a gate insulating film and a gate electrode; a p-type high-concentration well region formed parallel to the trench with a spacing therefrom and that has a depth larger than that of the trench; and a p-type body region formed to have a depth that gradually increases when nearing from a position upward from the bottom end of the trench by approximately the thickness of the gate insulating film at the bottom of the trench toward the lower end of the p-type high-concentration well region.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 24, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Yasuhiro Kagawa, Shiro Hino, Naruhisa Miura, Masayuki Imaizumi
  • Publication number: 20170309711
    Abstract: An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.
    Type: Application
    Filed: July 11, 2017
    Publication date: October 26, 2017
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro KAGAWA, Rina TANAKA, Yutaka FUKUI, Naruhisa MIURA, Yuji ABE, Masayuki IMAIZUMI
  • Patent number: 9741797
    Abstract: An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: August 22, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui, Naruhisa Miura, Yuji Abe, Masayuki Imaizumi
  • Publication number: 20170162649
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro KAGAWA, Akihiko FURUKAWA, Shiro HINO, Hiroshi WATANABE, Masayuki IMAIZUMI
  • Patent number: 9614029
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: April 4, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuhiro Kagawa, Akihiko Furukawa, Shiro Hino, Hiroshi Watanabe, Masayuki Imaizumi
  • Patent number: 9577086
    Abstract: A device that increases a value of current flowing through a whole chip until a p-n diode in a unit cell close to a termination operates and reduces a size of the chip and a cost of the chip resulting from the reduced size. The device includes a second well region located to sandwich the entirety of a plurality of first well regions therein in plan view, a third separation region located to penetrate the second well region from a surface layer of the second well region in a depth direction, and a second Schottky electrode provided on the third separation region.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: February 21, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Masayuki Imaizumi, Kohei Ebihara
  • Patent number: 9525057
    Abstract: A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 20, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naruhisa Miura, Shiro Hino, Akihiko Furukawa, Yuji Abe, Shuhei Nakata, Masayuki Imaizumi, Yasuhiro Kagawa
  • Patent number: 9515145
    Abstract: A semiconductor device capable of reducing ON-resistance changes with temperature, including a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a first well region of a second conductivity type formed in the front surface of the drift layer, a second well region of the second conductivity type formed in the front surface of the drift layer, and a gate structure that is formed on the front surface of the drift layer and forms a channel in the first well region and a channel in the second well region. A channel resistance of the channel formed in the first well region has a temperature characteristic that the channel resistance decreases with increasing temperature and a channel resistance of the channel formed in the second well region has a temperature characteristic that the channel resistance increases with increasing temperature.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: December 6, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masayuki Furuhashi, Hiroaki Okabe, Tomokatsu Watanabe, Masayuki Imaizumi
  • Patent number: 9496344
    Abstract: In a JBS diode using a wide band gap semiconductor, the wide band gap semiconductor has a large built-in voltage, which sometimes causes difficulties for the pn diode portion to turn on, resulting in a problem that resistance to surge currents is not sufficiently ensured. In order to solve this problem, in the wide-band-gap JBS diode, a pn junction of the pn diode is formed away from the Schottky electrode, and well regions are formed so as to have a width narrowed at a portion away from the Schottky electrode.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 15, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Akihiko Furukawa, Masayuki Imaizumi, Yuji Abe
  • Publication number: 20160247894
    Abstract: A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.
    Type: Application
    Filed: September 2, 2014
    Publication date: August 25, 2016
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji HAMADA, Masayuki IMAIZUMI
  • Patent number: 9425261
    Abstract: A silicon carbide semiconductor device that reduces an influence of an off-angle of a silicon carbide substrate on characteristics of the semiconductor device and achieves improved operational stability and reduced resistance. In a trench-gate silicon carbide MOSFET semiconductor device, a high-concentration well region is formed in a well region, and a distance from a first sidewall surface of a trench of the silicon carbide semiconductor to the high-concentration well region is smaller than a distance from a second sidewall surface of the trench to the high-concentration well region, the second sidewall surface facing the first sidewall surface of the trench through the gate electrode.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: August 23, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yutaka Fukui, Yasuhiro Kagawa, Rina Tanaka, Yuji Abe, Masayuki Imaizumi
  • Patent number: 9362391
    Abstract: It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: June 7, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoichiro Tarui, Eisuke Suekawa, Naoki Yutani, Shiro Hino, Naruhisa Miura, Masayuki Imaizumi
  • Patent number: 9337271
    Abstract: It is an object of the present invention to provide a silicon carbide semiconductor device that reduces an influence of an off-angle of a silicon carbide substrate on characteristics of the semiconductor device and achieves improved operational stability and reduced resistance. In a trench-gate silicon carbide MOSFET semiconductor device formed on the silicon carbide semiconductor substrate having the off-angle, a low-channel doped region is provided on a first sidewall surface side of the trench in a well region, and a high-channel doped region having an effective acceptor concentration lower than that of the low-channel doped region is provided on a second sidewall surface side of the trench in the well region.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 10, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yutaka Fukui, Yasuhiro Kagawa, Rina Tanaka, Yuji Abe, Masayuki Imaizumi