Patents by Inventor Masayuki Imaizumi
Masayuki Imaizumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120074508Abstract: A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.Type: ApplicationFiled: December 1, 2011Publication date: March 29, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kenichi OHTSUKA, Naruhisa Miura, Masayuki Imaizumi, Tatsuo Oomori
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Publication number: 20120009801Abstract: In a silicon carbide MOSFET, interface state generated at an interface between a silicon carbide layer and a gate insulating film cannot be reduced sufficiently, and mobility of a carrier is decreased. To solve this problem, a silicon carbide semiconductor device according to this invention includes a substrate introduction step of introducing a substrate, which includes a silicon carbide layer on which a gate insulating film is formed, in a furnace, and a heating step of heating the furnace having the substrate introduced therein while introducing nitrogen monoxide and nitrogen therein, wherein, in the heating step, nitrogen is reacted to nitride an interface between the gate insulating film and the silicon carbide layer.Type: ApplicationFiled: March 10, 2010Publication date: January 12, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Toshikazu Tanioka, Masayuki Furuhashi, Masayuki Imaizumi
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Patent number: 8093598Abstract: A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.Type: GrantFiled: March 19, 2007Date of Patent: January 10, 2012Assignee: Mitsubishi Electric CorporationInventors: Kenichi Ohtsuka, Naruhisa Miura, Masayuki Imaizumi, Tatsuo Oomori
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Publication number: 20110278599Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: ApplicationFiled: February 23, 2010Publication date: November 17, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
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Patent number: 8026160Abstract: In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers.Type: GrantFiled: May 9, 2006Date of Patent: September 27, 2011Assignee: Mitsubishi Electric CorporationInventors: Yoichiro Tarui, Ken-ichi Ohtsuka, Masayuki Imaizumi
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Patent number: 7928469Abstract: The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 2 of a MOSFET made of silicon carbide according to the present invention has a first region 2a and a second region 2b. The first region 2a is a region from the surface to a first given depth. The second region 2b is formed in a region deeper than the first given depth. The impurity concentration of the first region 2a is lower than the impurity concentration of the second region 2b.Type: GrantFiled: October 6, 2006Date of Patent: April 19, 2011Assignee: Mitsubishi Electric CorporationInventors: Keiko Fujihira, Naruhisa Miura, Kenichi Ohtsuka, Masayuki Imaizumi
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Publication number: 20110001209Abstract: In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage.Type: ApplicationFiled: March 12, 2009Publication date: January 6, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Hiroshi Watanabe, Naoki Yutani, Kenichi Ohtsuka, Kenichi Kuroda, Masayuki Imaizumi, Yoshinori Matsuno
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Publication number: 20100314629Abstract: In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.Type: ApplicationFiled: February 12, 2008Publication date: December 16, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro Tarui, Kenichi Ohtsuka, Naruhisa Miura, Yoshinori Matsuno, Masayuki Imaizumi
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Publication number: 20100219417Abstract: A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.Type: ApplicationFiled: November 17, 2006Publication date: September 2, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa Miura, Keiko Fujihira, Kenichi Otsuka, Masayuki Imaizumi
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Patent number: 7708029Abstract: A coupling member is provided that comprises a valve movable between a closed position and an opening position. The valve is provided with a seal ring fixed in an annular groove formed in the valve and urged against a valve seat in the closed position. The groove has a forward annular groove portion and a rear annular groove portion shallower than the forward annular groove portion. The seal ring has forward and rear annular seal portions fitted in the forward and rear annular groove portions, respectively. The rear ring portion has substantially the same diameter as the forward seal portion.Type: GrantFiled: June 27, 2007Date of Patent: May 4, 2010Assignee: Nitto Kohki Co., Ltd.Inventors: Hiroyuki Kitagawa, Masayuki Imaizumi, Koji Matsumoto
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Publication number: 20090261348Abstract: In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers.Type: ApplicationFiled: May 9, 2006Publication date: October 22, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro Tarui, Ken-ichi Ohtsuka, Masayuki Imaizumi
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Publication number: 20090250705Abstract: A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method for implantation at high temperatures is used. In terms of switching loss and the like of devices, it is desirable that the resistivity of the p base ohmic contact should be lower. In well-known techniques, nothing is mentioned on a detailed relation among the ion implantation temperature, the ohmic contact resistivity and the process failure. Then, in the ion implantation step, the temperature of a silicon carbide wafer is maintained in a range from 175° C. to 300° C., more preferably in a range from 175° C. to 200° C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175° C. to 300° C.Type: ApplicationFiled: November 7, 2008Publication date: October 8, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Tomokatsu WATANABE, Sunao Aya, Naruhisa Miura, Keiko Sakai, Shohei Yoshida, Toshikazu Tanioka, Yukiyasu Nakao, Yoichiro Tarui, Masayuki Imaizumi
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Publication number: 20090173997Abstract: The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 2 of a MOSFET made of silicon carbide according to the present invention has a first region 2a and a second region 2b. The first region 2a is a region from the surface to a first given depth. The second region 2b is formed in a region deeper than the first given depth. The impurity concentration of the first region 2a is lower than the impurity concentration of the second region 2b.Type: ApplicationFiled: October 6, 2006Publication date: July 9, 2009Applicant: Mitsubishi Electric CorporationInventors: Keiko Fujihira, Naruhisa Miura, Kenichi Ohtsuka, Masayuki Imaizumi
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Publication number: 20090020766Abstract: A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.Type: ApplicationFiled: March 19, 2007Publication date: January 22, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kenichi Ohtsuka, Naruhisa Miura, Masayuki Imaizumi, Tatsuo Oomori
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Publication number: 20070246107Abstract: A seal ring of an on-off valve of a pipe coupling is prevented from separating from the on-off valve even when a fluid flows at high speed around the seal ring. When an on-off valve 26 is in the closed position, a seal ring 50 is sealingly engaged under pressure with an annular valve seat surface 34. A forward annular valve surface portion 52 located forward of the seal ring and a rear annular valve surface portion 54 at the rear of the seal ring respectively have a forward annular passage limiting portion 56 and a rear annular passage limiting portion 58 that are adapted to be in contact with or close proximity to the annular valve seat surface. During the period from when the on-off valve starts to move from the closed position (FIG. 4) toward the open position (FIG.Type: ApplicationFiled: June 27, 2007Publication date: October 25, 2007Applicant: NITTO KOHKI CO., LTD.Inventors: Hiroyuki Kitagawa, Masayuki Imaizumi, Koji Matsumoto
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Patent number: 7285465Abstract: A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET that uses SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.Type: GrantFiled: February 15, 2006Date of Patent: October 23, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoichiro Tarui, Ken-ichi Ohtsuka, Masayuki Imaizumi, Hiroshi Sugimoto, Tetsuya Takami
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Publication number: 20060134847Abstract: A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET that uses SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.Type: ApplicationFiled: February 15, 2006Publication date: June 22, 2006Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Yoichiro Tarui, Ken-ichi Ohtsuka, Masayuki Imaizumi, Hiroshi Sugimoto, Tetsuya Takami
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Patent number: 7029969Abstract: A semiconductor device and its manufacturing method in which the trade-off relationship between channel resistance and JFET resistance is improved. The same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET including SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.Type: GrantFiled: March 18, 2004Date of Patent: April 18, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoichiro Tarui, Ken-ichi Ohtsuka, Masayuki Imaizumi, Hiroshi Sugimoto, Tetsuya Takami
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Publication number: 20040188755Abstract: A semiconductor device and its manufacturing method in which the trade-off relationship between channel resistance and JFET resistance is improved. The same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET including SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.Type: ApplicationFiled: March 18, 2004Publication date: September 30, 2004Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Yoichiro Tarui, Ken-ichi Ohtsuka, Masayuki Imaizumi, Hiroshi Sugimoto, Tetsuya Takami