Abstract: A photographic device equipped with a camera capable of photographing a 360-degree all-round image at a time includes a memory for recording the all-round image photographed by the camera, a control unit for specifying a predetermined range within the all-round image, extracting an image of the predetermined range from the memory to display the image, and for extracting and displaying the image within the all-round image recorded in the memory by changing a position of the predetermined range, thereby displaying the image as if the predetermined range moves in a circumferential direction, and a display unit for displaying at least the image of the predetermined range.

Abstract: Provided is a specific configuration of an omnidirectional photographing device which includes one camera module equipped with a lens for directly taking a 360-degree annular image. More specifically, there is provided an omnidirectional photographing device configured to facilitate carrying. The omnidirectional photographing device includes: one camera module equipped with a lens capable of directly taking a 360-degree annular image; a main body for holding the camera module; and a display unit fixed to the main body, for displaying an image photographed by the camera module.

Abstract: Provided are novel compounds having an inhibitory activity against production or secretion of ?-amyloid protein. They embrace compounds represented by the following formula (1): and capable of being replaced with a variety of substituents; and salts thereof, and solvates of any one of them.

Abstract: A web load test program is used to display information about responses acquired by applying access load on a web server device as a test target. The program generates a plurality of virtual web clients each of which transmits a request message to the web server device and receives a response message from the web server device in order according to a given scenario. The program stores a log information record containing ID of the virtual web client that receives a response message and order information that shows an order of the request in the scenario corresponding to the response message into storage whenever the virtual web client receives a response message from the web server device. The program sorts the log information records that are linked with the respective response messages according to a predetermined sort condition and displays the sorted log information records onto a display.

Abstract: In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P0), which is subjected to the address translation by TLB, and areas (P1 and P2), which are fixedly mapped to the physical address without being subjected the address translation, future extension of the physical address become difficult. A data processor comprises an address translation unit ATU that receives virtual address output from the CPU and outputs a physical address; the ATU includes a first translation lookaside buffer UTLB, a second translation lookaside buffer DTLB, a control circuit TLB_CTL that selects one of a first and a second translation lookaside buffers and performs address translation in accordance with an area of an address space in the virtual address.

Abstract: A load simulator is used to apply access load on a web server device as a test target using a plurality of virtual web clients each of which transmits a request message and receives a response message in order according to a given scenario. The load simulator makes a computer function as search means for searching page data of a response message for predetermined character strings when a virtual web client receives the response message from the web server device through a communication device, source modifying means for overwriting the predetermined character string searched by the search means by replacing characters of a part of the string to disable a function provided by the original character string, and output means for passing the page data that is overwritten by the source modifying means to the viewer.

Abstract: The web load test method makes a computer function as virtual web client generation means for generating a plurality of virtual web clients each of which transmits a request message to the web server device and receives a response message according to a scenario; memory means for storing synchronous point information that specifies an order in the scenario of the response message, which should be a synchronous point among the response messages, into storage; waiting means for interrupting the accesses by the clients until the time when all the clients receive the response messages whose orders are indicated by the synchronous point information; resumption means for resuming the accesses when all the clients receive the response messages whose orders are indicated by the synchronous point information; and rewrite means for replacing the synchronous point information stored in the storage with synchronous point information that specifies another response message.

Abstract: Disclosed is a scenario generation program that is used to generate a scenario given to a plurality of virtual web clients each of which applies access load to a web server device of a test target. According to the program, a computer stores some first request messages transmitted to a web server device and some second request messages transmitted to the web server device based on the same operation. The computer extracts the differences between the request parameters in the first and second request messages in the same order of the same operation. If page data of a response message includes the extracted request parameters, rewriting-item information is generated corresponding to the request parameter and is incorporated into the scenario. The computer replace the parameter shown by the rewriting-item information whenever the computer executes the scenario.

Abstract: A medium detecting apparatus and an image forming apparatus are supplied capable of making medium move without hitting sensor lever while skew adjustment or medium setting operation. In the image forming apparatus, a medium hit surface of the sensor lever to detect skew holds inclinations in plural directions and a guider to limit the medium is furnished on the inclined side; or a medium hit surface of the sensor lever to detect skew holds inclinations in plural directions and position detections in movement direction of carriage and in conveyance direction of medium are performed by one sensor; or a sheet guider is further furnished and the sensor lever whose medium hit surface holds inclinations in plural directions is used as a sensor to detect a paper setting; or a hand-operated adjustment print function is further furnished and the sensor lever whose medium hit surface holds inclinations in plural directions is used as a sensor to detect a paper setting.

Abstract: In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P0), which is subjected to the address translation by TLB, and areas (P1 and P2), which are fixedly mapped to the physical address without being subjected the address translation, future extension of the physical address become difficult. A data processor comprises an address translation unit ATU that receives virtual address output from the CPU and outputs a physical address; the ATU includes a first translation lookaside buffer UTLB, a second translation lookaside buffer DTLB, a control circuit TLB_CTL that selects one of a first and a second translation lookaside buffers and performs address translation in accordance with an area of an address space in the virtual address.

Abstract: A photographic device including: a wide-angle lens; an image processing unit for processing light passed through the wide-angle lens to convert the light into a wide-field picture, directly cutting out a part of the wide-field picture, and for correcting distortion of the part cut out; and recording means capable of recording the picture corrected for distortion by the image processing unit.

Abstract: A processing load of a high performance application processing such as a voice, an image and the like is reduced, and a processing capacity of a base band processing is improved. A semiconductor integrated circuit device used in a mobile communication system such as a cellular phone is provided with a base band CPU block performing a base band processing for executing a base band protocol stack, an application system CPU block executing a high-level OS and controlling applications other than the base band processing, an application real-time CPU block executing a real-time OS and the like and controlling an image/voice processing, all of which are formed on one semiconductor chip. Further, internal high-speed buses to which these CPU blocks are connected are respectively connected via bridges.

Abstract: A light source module of the present invention includes: a first luminous element for emitting light having two peak wavelengths; and a second luminous element for emitting light having a single peak wavelength. With this configuration, it is possible to downsize the light source module, and improve a color reproducibility via a color filter.

Abstract: Provided are novel compounds having an inhibitory activity against production or secretion of ?-amyloid protein. They embrace compounds represented by the following formula (1): and capable of being replaced with a variety of substituents; and salts thereof, and solvates of any one of them.

Abstract: A load test apparatus includes a computer which is implemented with an operating system having a window management function, and can be connected to a network device to be tested through an information network, and a terminal emulation program used to direct a computer to perform a first function for providing an execution environment in an MDI system of an application in a plurality of virtual terminals in a first window, and a second function capable of generating a plurality of second windows which cannot be discriminated by the window management function in the first window by managing independently from the operating system the second window generated in the first window. The terminal emulation program is executed by the computer to access to the network device from the plurality of virtual terminals, thereby conducting a load test.

Abstract: A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory (5) and an external memory (25,26). When an address specified by the addressing field coincides with an address mapped to the internal memory, the particular instruction sets a logical address as one of the transfer source or transfer destination addresses of the data block transfer. The internal memory is allotted to a part of virtual address space; the internal memory allotted so is associated with the physical address space, to which the external memory set as the other address is allotted, by a process in which a TLB is used when the MMU is in ON, and a given register is used when the MMU is in OFF.

Abstract: An apparatus having a band-separating filter bank for separating a digital signal into a plurality of sub-band signals, to be processed or transmitted, and a band-combining filter bank for subsequently combining the resultant sub-band signals into a single digital signal, wherein each of the band-separating filter bank and band-combining filter bank incorporates a FIR low pass filter having an asymmetric impulse response, as the prototype filter of the filter bank. A significant reduction can thereby be achieved in the amount of overall group delay that results from the processing performed by these filter banks.

Abstract: The data processor has a set-associative cache memory capable of performing associative operation using tag information for an indexed cache line. The cache memory includes way prediction part for performing a selection of a way based on the prediction in parallel with the associative operation, generation part for generating way selection determining information based on the associative operation using the subsequent access address during a penalty cycle caused by a prediction miss of the way prediction part, and control part for making a way selected for the subsequent access address after the penalty cycle on the basis of the way selection determining information. Since a way to be hit at the subsequent cache access can be predetermined during the preceding penalty cycle, the cumulative number of penalty cycles can be reduced.

Abstract: In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P0), which is subjected to the address translation by TLB, and areas (P1 and P2), which are fixedly mapped to the physical address without being subjected the address translation, future extension of the physical address become difficult. A data processor comprises an address translation unit ATU that receives virtual address output from the CPU and outputs a physical address; the ATU includes a first translation lookaside buffer UTLB, a second translation lookaside buffer DTLB, a control circuit TLB_CTL that selects one of a first and a second translation lookaside buffers and performs address translation in accordance with an area of an address space in the virtual address.

Abstract: An apparatus having a band-separating filter bank for separating a digital signal into a plurality of sub-band signals, to be processed or transmitted, and a band-combining filter bank for subsequently combining the resultant sub-band signals into a single digital signal, wherein each of the band-separating filter bank and band-combining filter bank incorporates a FIR low pass filter having an asymmetric impulse response, as the prototype filter of the filter bank. A significant reduction can thereby be achieved in the amount of overall group delay that results from the processing performed by these filter banks.