Abstract: A user interface device which displays an operation key in a display unit using a predetermined design.

Abstract: An image processing apparatus which executes a predetermined image processing using a data file stored in a data storage device.

Abstract: A load simulator is used to apply access load on a web server device as a test target using a plurality of virtual web clients each of which transmits a request message and receives a response message in order according to a given scenario. The load simulator makes a computer function as search means for searching page data of a response message for predetermined character strings when a virtual web client receives the response message from the web server device through a communication device, source modifying means for overwriting the predetermined character string searched by the search means by replacing characters of a part of the string to disable a function provided by the original character string, and output means for passing the page data that is overwritten by the source modifying means to the viewer.

Abstract: A processing load of a high performance application processing such as a voice, an image and the like is reduced, and a processing capacity of a base band processing is improved. A semiconductor integrated circuit device used in a mobile communication system such as a cellular phone is provided with a base band CPU block performing a base band processing for executing a base band protocol stack, an application system CPU block executing a high-level OS and controlling applications other than the base band processing, an application real-time CPU block executing a real-time OS and the like and controlling an image/voice processing, all of which are formed on one semiconductor chip. Further, internal high-speed buses to which these CPU blocks are connected are respectively connected via bridges.

Abstract: A web load test program to display information about responses acquired by applying access load on a web server device as a test target is provided. The program generates a plurality of virtual web clients each of which transmits a request message to the web server device and receives a response message from the web server device in order according to a given scenario. The program stores a log information record containing an ID of the virtual web client that receives a response message and order information that shows an order of the request in the scenario corresponding to the response message into storage whenever the virtual web client receives a response message from the web server device. The program sorts the log information records that are linked with the respective response messages according to a predetermined sort condition and displays the sorted log information records onto a display.

Abstract: Provided is an insulated gate bipolar transistor (IGBT) which occupies a small area and in which a thermal breakdown is suppressed. The IGBT includes: an n-type semiconductor layer (3); and a collector part formed in a surface portion of the n-type semiconductor layer (3). The collector part includes: an n-type buffer region (14); and a p+-type collector region (15) and an n+-type contact region (18) which are formed in the n-type buffer region (14).

Abstract: An image processing apparatus includes a scanner for reading out documents, a first extraction unit for extracting text contained in document images, a second extraction unit for extracting at least one Web address from the text, a fetch unit for obtaining at least one Web page corresponding to the Web address, a first generation unit for generating a concatenated image by concatenating the document images with the Web page, and a second generation unit for generating an index indicating a corresponding relationship between the document images and the Web page in the concatenated image.

Abstract: Provided are a graphite material, which has excellent bonding characteristics to semiconductor and efficiently dissipates heat generated from the semiconductor, and a method for manufacturing such material. The graphite material is provided by adding at least two kinds of elements selected from among silicon, zirconium, calcium, titanium, chromium, manganese, iron, cobalt, nickel, calcium, yttrium, niobium, molybdenum, technetium, ruthenium and compounds containing such elements, and by performing heat treatment. The graphite material is characterized in having a thickness of the 112 face of the graphite crystal of 15 nm or more by X-ray diffraction, and an average heat conductivity of 250 W/(m·K) or more in the three directions of the X, Y and Z axes.

Abstract: Whether a USB icon button is pressed or not is determined. If determined, a USB device status table in a USB device monitoring unit is referred to. Based on information in the USB device status table, a rank determination is executed. After the rank determination, the priority to recommend disconnection from a USB connector is then set based on the rank determination result. Then, a USB device priority screen is displayed.

Abstract: Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed.

Abstract: It is determined whether or not a USB display button is pressed, and if so determined, a USB device status management table in a USB device status management part is referenced. Ranking determination is made based on information on the USB device status management table. After the ranking determination, priority is set based on the ranking determination result. Then, a USB device priority screen is displayed on a manipulation display of a manipulation panel part.

Abstract: The present invention relates to a novel compound having an effect of inhibiting production/secretion of ?-amyloid protein. The present invention provides a compound represented by the general formula (1): or a salt thereof, or a solvate of the compound or the salt; and a medicament comprising thereof.

Abstract: Provided is a specific configuration of an omnidirectional photographing device which includes one camera module equipped with a lens for directly taking a 360-degree annular image. More specifically, there is provided an omnidirectional photographing device configured to facilitate carrying. The omnidirectional photographing device includes: one camera module equipped with a lens capable of directly taking a 360-degree annular image; a main body for holding the camera module; and a display unit fixed to the main body, for displaying an image photographed by the camera module.

Abstract: A photographic device equipped with a camera capable of photographing a 360-degree all-round image at a time includes a memory for recording the all-round image photographed by the camera, a control unit for specifying a predetermined range within the all-round image, extracting an image of the predetermined range from the memory to display the image, and for extracting and displaying the image within the all-round image recorded in the memory by changing a position of the predetermined range, thereby displaying the image as if the predetermined range moves in a circumferential direction, and a display unit for displaying at least the image of the predetermined range.

Abstract: Provided is a semiconductor device that is capable of suppressing occurrence of a crystal defect in an elongated circuit region formed in an SOI substrate. Low-voltage transistor regions are separated, by multiple inner isolation layers, into multiple sub-regions. For this reason, the length of the longitudinal direction of the sub-regions is reduced, even though the low-voltage transistor regions are extremely elongated, for example. This configuration can suppress occurrence of a crystal defect in the low-voltage transistor regions in the longitudinal direction thereof, although such defect may occur due to the difference in thermal expansion or thermal contraction between a semiconductor layer in the low-voltage transistor regions, and the element isolation layers.

Abstract: A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory (5) and an external memory (25,26). When an address specified by the addressing field coincides with an address mapped to the internal memory, the particular instruction sets a logical address as one of the transfer source or transfer destination addresses of the data block transfer. The internal memory is allotted to a part of virtual address space; the internal memory allotted so is associated with the physical address space, to which the external memory set as the other address is allotted, by a process in which a TLB is used when the MMU is in ON, and a given register is used when the MMU is in OFF.

Abstract: A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory (5) and an external memory (25,26). When an address specified by the addressing field coincides with an address mapped to the internal memory, the particular instruction sets a logical address as one of the transfer source or transfer destination addresses of the data block transfer. The internal memory is allotted to a part of virtual address space; the internal memory allotted so is associated with the physical address space, to which the external memory set as the other address is allotted, by a process in which a TLB is used when the MMU is in ON, and a given register is used when the MMU is in OFF.

Abstract: Provided are novel compounds having an inhibitory activity against production or secretion of ?-amyloid protein. They embrace compounds represented by the following formula (1): and capable of being replaced with a variety of substituents; and salts thereof, and solvates of any one of them.

Abstract: An image processing apparatus is disclosed. The image processing apparatus includes a thinning-out section generating thinned-out line data of thinned-out data constituted by a plurality of the thinned-out line data, the thinned-out data being obtained by thinning out wide-field image data with distortion captured using a wide-angle lens, and sequentially outputting the thinned-out line data at every predetermined timing, a switching section performing switching from an output of the wide-field image data to an output of the thinned-out line data in response to the predetermined timing, and a buffer temporarily storing the wide-field image data and the thinned-out data constituted by the plurality of thinned-out data outputted after the switching.

Abstract: In regard to a set associative cache memory (21) having ways coincident in number with entries of TLB, the ways each have a storage capacity in its data part (DAT); the storage capacity corresponds to a page size, which is a unit of address translation by TLB. Each way has no tag memory as an address part nor tag. The entries (ETY0-ETY7) of TLB are in a one-to-one correspondence with ways (WAY0-WAY7) of the cache memory. Only the data in a region subjected to mapping to a physical address defined by an address translation pair of TLB can be cached in the corresponding way. According to a TLB hit signal produced with a logical product of the result of the comparison of a virtual page address of TLB and an effective bit of TLB, an action for a cache data array is selected for only one way. The cache effective bit of the way with the action selected is used as a cache hit signal.