Patents by Inventor Masayuki Koizumi

Masayuki Koizumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446422
    Abstract: A method is provided, the method including: repeatedly acquiring a state of one or more devices included in the semiconductor manufacturing apparatus; providing a first animation indicating an operation of the semiconductor manufacturing apparatus by displaying at least an image indicating the state of one or more devices on a display unit each time the state is acquired; storing, in a memory, the acquired state of one or more devices and a time related to the state; receiving an input for switching a display mode; and providing a second animation of the semiconductor manufacturing apparatus by displaying, one by one on the display unit, at least one or more images respectively indicating the state of one or more devices related to one or more times including a reference time stored in the memory, after receiving the input for switching a display mode.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 15, 2019
    Assignee: EBARA CORPORATION
    Inventors: Masayuki Fujiki, Hideharu Aoyama, Ryuya Koizumi
  • Publication number: 20180331684
    Abstract: A proximity sensor includes a transmission circuit that supplies a current to each of detection coils, a reception circuit that detects voltages generated at both ends of the coils or currents flowing in the coils due to the supply of the current for each of the coils, a control unit that senses the presence or position of a detection object using a detection result of the reception circuit, and an output unit that outputs a sensing result of the control unit. The control unit extracts a first component caused by a mounting fitting for mounting the proximity sensor on a support member and a second component caused by the detection object from the detection result of the reception circuit. The control unit compensates the second component using the first component. The control unit senses the presence or position of the detection object on the basis of the compensated second component.
    Type: Application
    Filed: February 8, 2018
    Publication date: November 15, 2018
    Applicant: OMRON Corporation
    Inventors: Masayuki KOIZUMI, Minami WAZUMI, Yusuke NAKAYAMA
  • Publication number: 20180267192
    Abstract: A proximity sensor includes a transmission circuit that periodically supplies an excitation current in a pulse form to a detection coil for generating a magnetic field, a reception circuit that detects voltages or currents generated at both ends of the detection coil by the periodic supply of the excitation current, and a controller that detects presence or a position of the detection body by utilizing a time series signal obtained by the detection. The controller acquires a factor that influences the detection of the detection body in a first period of the time series signal. The controller compensates a signal in a second period of the time series signal by the factor. The controller detects the presence or the position of the detection body on the basis of a signal after the compensation.
    Type: Application
    Filed: December 15, 2017
    Publication date: September 20, 2018
    Applicant: OMRON Corporation
    Inventors: Minami WAZUMI, Masayuki KOIZUMI, Yusuke NAKAYAMA
  • Publication number: 20180231398
    Abstract: A proximity sensor is provided with coils (11, 12) disposed in a pre-set positional relationship, a first distance calculation unit (31) and a second distance calculation unit (32) for calculating first distance information (d1) and second distance information (d2), respectively, from the coils (11, 12) to a detection object (W) on the basis of reception results (voltages V1, V2) of the coils (11, 12), and a position estimating unit (33) for estimating the position, such as distance and azimuth, of the detection object (W) on the basis of the first distance information (d1), the second distance information (d2), and the positional relationship of the coils (11, 12) .
    Type: Application
    Filed: January 6, 2017
    Publication date: August 16, 2018
    Applicant: OMRON Corporation
    Inventors: Masayuki KOIZUMI, Minami WAZUMI, Chunmei HUANG, Kenji HOMMA
  • Patent number: 9362923
    Abstract: A delay circuit includes units each of which includes a first delay element having a first input node and a first output node, a second delay element having a second input node and a second output node, and a third delay element between the first and second delay elements. The first output node of a first unit of the units is connected to the first input node of a second unit of the units. The second input node of the first unit is connected to the second output node of the second unit. A signal on the first input node of the first delay element of the first unit is output from the second output node of the second delay element of the first unit through the third delay element of the second unit.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: June 7, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Mizogami, Masayuki Koizumi
  • Publication number: 20160020774
    Abstract: A delay circuit includes units each of which includes a first delay element having a first input node and a first output node, a second delay element having a second input node and a second output node, and a third delay element between the first and second delay elements. The first output node of a first unit of the units is connected to the first input node of a second unit of the units. The second input node of the first unit is connected to the second output node of the second unit. A signal on the first input node of the first delay element of the first unit is output from the second output node of the second delay element of the first unit through the third delay element of the second unit.
    Type: Application
    Filed: March 10, 2015
    Publication date: January 21, 2016
    Inventors: Takayuki Mizogami, Masayuki Koizumi
  • Patent number: 8075034
    Abstract: A mounting structure for vehicle interior parts includes a console member and a shift panel having an upper panel and a lower panel. An insertion portion that is inserted into a dent formed in a rear end of the console member is provided on a rear end of the lower panel. Left and right outer side surfaces of the insertion portion of the lower panel and left and right inner side surfaces of the dent of the console member are configured to be engageable by inserting engaging projections into engaging recesses. The engaging recesses are provided so as to restrict movements of the engaging projections in their longitudinal direction, and to allow positional deviation of the engaging projections in the vertical direction.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: December 13, 2011
    Assignee: Toyota Shatai Kabushiki Kaisha
    Inventors: Masayuki Koizumi, Yusaku Furukawa
  • Publication number: 20110006557
    Abstract: A mounting structure for vehicle interior parts includes a console member and a shift panel having an upper panel and a lower panel. An insertion portion that is inserted into a dent formed in a rear end of the console member is provided on a rear end of the lower panel. Left and right outer side surfaces of the insertion portion of the lower panel and left and right inner side surfaces of the dent of the console member are configured to be engageable by inserting engaging projections into engaging recesses. The engaging recesses are provided so as to restrict movements of the engaging projections in their longitudinal direction, and to allow positional deviation of the engaging projections in the vertical direction.
    Type: Application
    Filed: May 8, 2009
    Publication date: January 13, 2011
    Applicant: TOYOTA SHATAI KABUSHIKI KAISHA
    Inventors: Masayuki Koizumi, Yusaku Furukawa
  • Patent number: 7468625
    Abstract: A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: December 23, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Koizumi, Hiroyuki Shibayama
  • Patent number: 7391263
    Abstract: An operational amplifier 1 is provided with differential amplifier 2, replica amplifier 3, voltage-current converting circuit 4, reference current source 5 and comparator 6. Differential amplifier 2 includes P-channel MOS transistors PT1 and PT2, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT1, NT2 and NT3. Replica amplifier 3 is identical in structure to differential amplifier and also includes P-channel MOS transistors PT11 and PT12, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT11, NT12 and NT13. Voltage-current converting circuit 4 converts output voltages of replica amplifier 3 to current Irep. Comparator 6 compares output current Irep of voltage-current converting circuit 4 with reference current Iref of reference current source 5 and supplies compared current Ico to differential amplifier 2 to keep bias current Ibias of differential amplifier 2 constant.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: June 24, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Koizumi, Hiroyuki Shibayama
  • Publication number: 20080012630
    Abstract: A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.
    Type: Application
    Filed: July 6, 2007
    Publication date: January 17, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki KOIZUMI, Hiroyuki Shibayama
  • Patent number: 7248100
    Abstract: A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: July 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Koizumi, Hiroyuki Shibayama
  • Publication number: 20070057724
    Abstract: An operational amplifier 1 is provided with differential amplifier 2, replica amplifier 3, voltage-current converting circuit 4, reference current source 5 and comparator 6. Differential amplifier 2 includes P-channel MOS transistors PT1 and PT2, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT1, NT2 and NT3. Replica amplifier 3 is identical in structure to differential amplifier and also includes P-channel MOS transistors PT11 and PT12, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT11, NT12 and NT13. Voltage-current converting circuit 4 converts output voltages of replica amplifier 3 to current Irep. Comparator 6 compares output current Irep of voltage-current converting circuit 4 with reference current Iref of reference current source 5 and supplies compared current Ico to differential amplifier 2 to keep bias current Ibias of differential amplifier 2 constant.
    Type: Application
    Filed: August 29, 2006
    Publication date: March 15, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Koizumi, Hiroyuki Shibayama
  • Patent number: 7109771
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: September 19, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Patent number: 7088161
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: August 8, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20060001481
    Abstract: A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 5, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Koizumi, Hiroyuki Shibayama
  • Patent number: 6861882
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20050035802
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 17, 2005
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20050035803
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Application
    Filed: September 23, 2004
    Publication date: February 17, 2005
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Patent number: 6750680
    Abstract: There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced. In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: June 15, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidemasa Zama, Masayuki Koizumi, Yukiko Ito, Kimiyoshi Usami, Naoyuki Kawabe, Masahiro Kanazawa, Toshiyuki Furusawa