Abstract: An operational amplifier 1 is provided with differential amplifier 2, replica amplifier 3, voltage-current converting circuit 4, reference current source 5 and comparator 6. Differential amplifier 2 includes P-channel MOS transistors PT1 and PT2, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT1, NT2 and NT3. Replica amplifier 3 is identical in structure to differential amplifier and also includes P-channel MOS transistors PT11 and PT12, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT11, NT12 and NT13. Voltage-current converting circuit 4 converts output voltages of replica amplifier 3 to current Irep. Comparator 6 compares output current Irep of voltage-current converting circuit 4 with reference current Iref of reference current source 5 and supplies compared current Ico to differential amplifier 2 to keep bias current Ibias of differential amplifier 2 constant.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced. In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: An automatic circuit generation methods and apparatus (1) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.

Abstract: A semiconductor memory has paired first and second bit lines one of which passes a current representing data stored in a selected memory cell. If the first bit line transfers the current representing the data stored in the memory cell, the second bit line transfers a current representing data stored in a dummy cell. If the second bit line transfers the current representing the data stored in the memory cell, the first bit line transfers the current representing the data stored in the dummy cell. The current transferred through the first bit line is divided into partial currents, and the current transferred through the second bit line is also divided into partial currents. It is determined whether or not the current representing the data stored in the memory cell is passed through the first bit line.

Abstract: A semiconductor memory has paired first and second bit lines one of which passes a current representing data stored in a selected memory cell. If the first bit line transfers the current representing the data stored in the memory cell, the second bit line transfers a current representing data stored in a dummy cell. If the second bit line transfers the current representing the data stored in the memory cell, the first bit line transfers the current representing the data stored in the dummy cell. The current transferred through the first bit line is divided into partial currents, and the current transferred through the second bit line is also divided into partial currents. It is determined whether or not the current representing the data stored in the memory cell is passed through the first bit line.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced.

Abstract: An automatic circuit generation methods and apparatus (1) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.

Abstract: A booth decoder decodes A or −A according to a booth algorithm, depending upon whether A×B or −A×B should be multiplied. A partial multiplier/partial adder circuit 30 generates partial products of A×B or −A×B following to a result of the decoding, and sequentially adds these partial products. Data C, or data made by inverting bits of C, is input to the partial multiplier/partial adder circuit 30, depending upon whether C should be added or −C should be added to the result of multiplication. Also the data C or data made by inverting bits of C are sequentially added by the partial multiplier/partial adder circuit 30. A final adder circuit 50 executes final addition of these partial products, and adds 1 when −C should be added. Thus, Z=±(A×B)±C (the order of signs being variable) can be calculated.

Abstract: First and second well regions of N conductivity type are formed in a P-type semiconductor substrate. A digital circuit is formed in the first well region. An analog circuit is formed in the second well region. A power source wiring for supplying a bias potential is connected to the substrate. The power source wiring is connected to a power source terminal which is different from the power source terminal of the digital circuit.

Abstract: A semiconductor memory device comprises a memory cell array including NAND type memory cell units arranged in matrix and having a plurality of dynamic type memory cells connected in series, a plurality of word lines, a plurality of bit lines arranged within the memory cell array, the plurality of bit lines including a bit line pairs which are arranged adjacent to each other or between which at least one bit line is interposed, and a plurality of sense amplifiers of a folded bit line type, provided in each of the plurality of bit line pairs, in which the memory cells are provided in positions corresponding to intersections of the bit lines and the word lines, and complementary data are written to two memory cells connected to each of the plurality of bit line pairs and one word line, and the two memory cells store one-bit data.

Abstract: The present invention discloses an output circuit which comprises an input terminal for receiving an input signal having a predetermined logic level, an output terminal held at a potential corresponding to the logic level of the input signal, first and second power sources, separated from each other, third and fourth power sources, separated from each other, a fast potential changing circuit, which is connected between the first and third power sources, for instantaneously changing the potential at said output terminal when a logic level of the input signal changes, potential maintaining circuit connected between said second and fourth power sources, for maintaining the potential of the output terminal at the same level after the potential is changed by the rapid potential changing circuit, a first controlling circuit for controlling the fast potential changing circuit such that the fast potential changing circuit starts operating when the logic level of the input signal changes and stops operating after a pr