Abstract: The disclosure provides a vehicle body rear structure, which can reduce damage to the vehicle during a collision from the rear. The vehicle body rear structure includes a chassis rear, a hook reinforcement part fixed to a lower surface of the chassis rear; and a hook fixed on a back side of the chassis rear through the hook reinforcement part, in which the hook reinforcement part includes a plurality of part members independent from each other, the plurality of part members are connected in series and joined in a front-back direction of the vehicle to form a joint boundary part, and the joint boundary part is disposed with a weakened part on a side close to the chassis rear.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes placing a first semiconductor element on a wiring board, forming a first mask having an opening on the wiring board so that the first semiconductor element is positioned in the opening, putting a liquid first resin precursor into the opening of the first mask, curing the first resin precursor to obtain a first resin layer, and then removing the first mask.

Abstract: A semiconductor device includes: a wiring substrate; at least one first semiconductor element provided above the wiring substrate; a first resin layer configured to seal the first semiconductor element; and a second resin layer provided on an outer surface of the first resin layer. A Young's modulus of the second resin layer is greater than a Young's modulus of the first resin layer, and/or a linear thermal expansion coefficient of the second resin layer is greater than a linear thermal expansion coefficient of the first resin layer.

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

Abstract: In a semiconductor device, a substrate has a main surface. A first semiconductor chip has a first front surface and a first back surface, and is mounted on the main surface via a plurality of bump electrodes. A first spacer has a second front surface and a second back surface that is mounted on the main surface. A height of the second front surface from the main surface is within a range between a highest height and a lowest height of the first back surface from the main surface. A second spacer has a third front surface and a third back surface that is mounted on the main surface. A height of the third front surface from the main surface is within the range between the highest height and the lowest height of the first back surface from the main surface.

Abstract: A semiconductor device according to the present disclosure includes: a semiconductor chip including a first supply terminal and a second supply terminal; a passive element provided on the semiconductor chip, the passive element including a first electrode, a dielectric provided on the first electrode, and a second electrode provided on the dielectric; a first wiring which electrically connects the first supply terminal and the first electrode to each other; and a second wiring which electrically connects the second supply terminal and the second electrode to each other.

Abstract: According to one embodiment, a wafer includes a substrate including a first region and a second region that do not overlap each other; a first chip unit and a second chip unit each arranged on the substrate; a first electrode and a second electrode each electrically connected to the first chip unit; and a third electrode and a fourth electrode each electrically connected to the second chip unit. The first electrode and the third electrode are arranged in the first region. The second electrode and the fourth electrode are arranged in the second region. The first region is independent of a region in which the first chip unit and the second chip unit are provided.

Abstract: A semiconductor device includes: a wiring substrate in which a wiring layer is provided; a first semiconductor chip that is provided above the wiring substrate and on a surface of which a first pad is formed, the surface being on a side closer to the wiring substrate; a second semiconductor chip that is provided on the first semiconductor chip through a first resin layer and on a surface of which a second pad is formed, the surface being on a side opposite the wiring substrate; a third semiconductor chip that is provided on the second semiconductor chip through a second resin layer and on a surface of which a third pad is formed, the surface being on the side closer to the wiring substrate; and a first wire connecting the first pad and the third pad; and a second wire connecting the second pad and the wiring substrate.

Abstract: A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector is provided. The method includes detaching the semiconductor memory chip from the connector, performing an annealing process with respect to the semiconductor memory chip detached from the connector, and after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.

Abstract: A semiconductor device includes a first stacked body provided above a substrate, and including a plurality of first semiconductor chips stacked on top of one another; and a second stacked body provided further above the first stacked body, and including a plurality of second semiconductor chips stacked on top of one another. The first semiconductor chips each have a first pad facing toward the substrate, and the second semiconductor chips each have a second pad facing away from the substrate.

Abstract: A semiconductor device includes a first stacked body including a plurality of first semiconductor chips stacked along a first direction, each of the first semiconductor chips being offset from the other first semiconductor chips along a second direction perpendicular to the first direction; a first columnar electrode connected to an electrode pad of the first stacked body, and extending in the first direction; a second stacked body including a plurality of second semiconductor chips stacked along the first direction, each of the second semiconductor chips being offset from the other second semiconductor chips along the second direction, the second stacked body having a height larger than the first stacked body and overlap at least a portion of the first stacked body when viewed from the top; and a second columnar electrode connected to an electrode pad of the second stacked body, and extending in the first direction.

Abstract: A semiconductor device includes a first stacked body including first semiconductor chips stacked in a first direction and offset relative to each other in a second direction; a first columnar electrode coupled to the first semiconductor chip and extending in the first direction; a second stacked body arranged relative to the first stacked body in the second direction and including second semiconductor chips stacked in the first direction and offset relative to each other in the second direction; a second columnar electrode coupled to the second semiconductor chip and extending in the first direction; and a third semiconductor chip arranged substantially equally spaced to the first columnar electrode and the second columnar electrode.

Abstract: A semiconductor device includes a wiring substrate inside which a wiring layer is provided, a plurality of first semiconductor chips stacked in a shifted manner on the wiring substrate and each provided with a connection terminal on a surface facing the wiring substrate, and a second semiconductor chip having a function different from functions of the first semiconductor chips and provided on the wiring substrate on a side where the connection terminals are electrically connected to the wiring substrate.

Abstract: A semiconductor device includes: a printed wiring substrate; a semiconductor chip mounted on a first surface of the printed wiring substrate; a sealing resin sealing the semiconductor chip on the first surface of the printed wiring substrate; an electrode pad provided on a second surface on a side opposite to the first surface of the printed wiring substrate; an electrode terminal connected to the electrode pad and protruding from the second surface; and a metal layer provided on a surface of the electrode pad on the electrode terminal side or on the side opposite to the electrode terminal so as to straddle a boundary line of the bonding surface between the electrode terminal and the electrode pad which is at least a boundary line on a side facing an outside of a mounting region of the semiconductor chip.

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of ?40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of ?40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0?t1<t2.

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0?t1<t2.