Patents by Inventor Masayuki Miura

Masayuki Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10996002
    Abstract: An evaporator evaporates a working fluid by heat from a battery. The evaporator includes at least one evaporation channel connected to the battery in a thermally conductive manner. The evaporator includes a supply channel connected to an upstream end of the evaporation channel, and supplies the working fluid in liquid phase from the supply channel to the evaporation channel. The evaporator includes an outflow channel connected with a downstream end of the evaporation channel, and discharges the working fluid. The outflow channel is disposed above the supply channel, and the supply channel is disposed at a position more insulated from the heat of the battery than the evaporation channel is.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: May 4, 2021
    Assignee: DENSO CORPORATION
    Inventors: Yasumitsu Omi, Takeshi Yoshinori, Masayuki Takeuchi, Koji Miura
  • Patent number: 10989447
    Abstract: A refrigeration cycle device includes a compressor, a condenser, a first decompressor, an outside heat exchanger, and an evaporator. A predetermined part of a refrigerant passage from the condenser to the first decompressor through which the refrigerant flows is a condenser outlet portion. A predetermined part of a refrigerant passage from the first decompressor to the outside heat exchanger through which the refrigerant flows is an outside heat exchanger inlet portion. A predetermined part of a refrigerant passage from the outside heat exchanger to the second decompressor through which the refrigerant flows is an outside heat exchanger outlet portion. A volume capacity of the condenser outlet portion is larger than a volume capacity of the outside heat exchanger inlet portion. According to the refrigeration cycle device, preferable coefficient of performance of cycle can be achieved in different operation modes.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: April 27, 2021
    Assignee: DENSO CORPORATION
    Inventors: Koji Miura, Yoshiki Kato, Masayuki Takeuchi, Nobuyuki Hashimura, Keigo Sato, Norihiko Enomoto, Kengo Sugimura, Ariel Marasigan
  • Publication number: 20210082895
    Abstract: In a semiconductor device, a substrate has a main surface. A first semiconductor chip has a first front surface and a first back surface, and is mounted on the main surface via a plurality of bump electrodes. A first spacer has a second front surface and a second back surface that is mounted on the main surface. A height of the second front surface from the main surface is within a range between a highest height and a lowest height of the first back surface from the main surface. A second spacer has a third front surface and a third back surface that is mounted on the main surface. A height of the third front surface from the main surface is within the range between the highest height and the lowest height of the first back surface from the main surface.
    Type: Application
    Filed: February 5, 2020
    Publication date: March 18, 2021
    Applicant: KIOXIA CORPORATION
    Inventor: Masayuki MIURA
  • Patent number: 10946460
    Abstract: A splitting apparatus includes: a lower mold configured to allow placement of a plate material on the lower mold and arranged on a first side with respect to a split target line of the plate material; an upper blade configured to be raised or lowered with respect to the lower mold; and a support member arranged on a second side with respect to the split target line of the plate material. The splitting apparatus is configured that, in a case where the upper blade is lowered with respect to the lower mold in a state where the plate material is supported by the lower mold and the support member, a cut is formed on the split target line of the plate material by the upper blade, a crack is formed in conjunction with formation of the cut, and the plate material is split along the split target line.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 16, 2021
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Nobuyuki Sakakibara, Masayuki Miura, Takahiro Hashimoto
  • Patent number: 10943844
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki, Masatoshi Kawato, Masayuki Miura, Masatoshi Fukuda, Soichi Homma
  • Patent number: 10854576
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Masayuki Miura, Naoyuki Komuta, Yuka Akahane, Yukifumi Oyama
  • Publication number: 20200038976
    Abstract: A splitting apparatus includes: a lower mold configured to allow placement of a plate material on the lower mold and arranged on a first side with respect to a split target line of the plate material; an upper blade configured to be raised or lowered with respect to the lower mold; and a support member arranged on a second side with respect to the split target line of the plate material. The splitting apparatus is configured that, in a case where the upper blade is lowered with respect to the lower mold in a state where the plate material is supported by the lower mold and the support member, a cut is formed on the split target line of the plate material by the upper blade, a crack is formed in conjunction with formation of the cut, and the plate material is split along the split target line.
    Type: Application
    Filed: May 30, 2019
    Publication date: February 6, 2020
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Nobuyuki Sakakibara, Masayuki Miura, Takahiro Hashimoto
  • Publication number: 20190393114
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.
    Type: Application
    Filed: February 5, 2019
    Publication date: December 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Satoshi TSUKIYAMA, Hideo AOKI, Masatoshi KAWATO, Masayuki MIURA, Masatoshi FUKUDA, Soichi HOMMA
  • Patent number: 10347603
    Abstract: A semiconductor device manufacturing apparatus includes a stage, a head section facing the stage and configured to hold a semiconductor element, a driving section configured to drive one of the head section and the stage to move in a first direction intersecting the head section and the stage and apply a load to the other one of the stage and the head section, a load sensor configured to sense a load value of the applied load, and a controller configured to control the driving section to move one of the head section and the stage, and then separate the head section from the stage in accordance with a change in the load value.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: July 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masayuki Miura
  • Publication number: 20190036807
    Abstract: [OBJECT] To provide a network system which makes it possible to reduce the occurrence of a delay in data packet transfer processing even if periodic processing occurs. [ORGANIZATION] In a network system having a plurality of communication devices 10-1 to 10-5, the communication devices each include: an executing means (control part 12) that executes periodic processing whose processing occurs periodically; and an adjusting means (control part 12) that adjusts an execution timing at which the periodic processing is executed by the executing means, according to states of the other communication devices.
    Type: Application
    Filed: September 27, 2018
    Publication date: January 31, 2019
    Inventors: Masahiro RIKISO, Atsushi KUMAGAI, Yuto TSUJI, Masayuki MIURA
  • Publication number: 20190007299
    Abstract: A buffer capacity of a memory is reduced and the occurrence of useless communication is prevented.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 3, 2019
    Inventors: Masahiro RIKISO, Masayuki MIURA
  • Publication number: 20180261574
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Application
    Filed: September 3, 2017
    Publication date: September 13, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Masayuki MIURA, Naoyuki KOMUTA, Yuka AKAHANE, Yukifumi OYAMA
  • Patent number: 9647939
    Abstract: Provided are a communication device and a communication system in which multi-hop communication is possible and management of communication routes is easy. In a distribution-system communication device 100, a port management means 132 is provided in a communication control unit 130, and each of ports provided in a port section 110 can be managed with the port management means 132 by IP addresses of adjacent stations connected to each of the ports. In a port management means 132 of a master station, correspondence information between port numbers of the port section 110 of each of the slave stations and the IP addresses of adjacent stations of a connection destination is input from the port management means 132 of each of the slave stations, and connection states between the ports of each of the slave stations can be managed based on the correspondence information.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: May 9, 2017
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Atsushi Kumagai, Kunio Odaka, Masayuki Miura, Kazutaka Shimoosako
  • Publication number: 20160336291
    Abstract: A semiconductor device manufacturing apparatus includes a stage, a head section facing the stage and configured to hold a semiconductor element, a driving section configured to drive one of the head section and the stage to move in a first direction intersecting the head section and the stage and apply a load to the other one of the stage and the head section, a load sensor configured to sense a load value of the applied load, and a controller configured to control the driving section to move one of the head section and the stage, and then separate the head section from the stage in accordance with a change in the load value.
    Type: Application
    Filed: March 4, 2016
    Publication date: November 17, 2016
    Inventor: Masayuki MIURA
  • Patent number: 9325606
    Abstract: A communication system that performs communication route control includes a center node and at least one node connected thereto via a communication line. The node includes an error-detecting unit that detects an error in the communication route, a route request packet transmitting unit that broadcasts a new route request packet in response to the detection, a route answer packet receiving unit that receives a route answer packet transmitted from a node that is a target node or a node having a valid route to the target node or from the center node, and a communication route updating unit that updates a communication route based on the route answer packet. A node that is the target node or the node having a valid route to the target node or the center node transmits a route answer packet to the node in response to a route request packet transmitted from the node.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: April 26, 2016
    Assignee: Furukawa Electric Co., Ltd
    Inventors: Atsushi Kumagai, Masayuki Miura, Kunio Odaka, Kazutaka Shimoosako
  • Publication number: 20150115042
    Abstract: A contactless information medium includes: a body forming an outer shape of the contactless information medium; an IC chip housed in the body; a coil antenna which is formed of a string of conductive wire, both ends of the conductive wire being connected to the IC chip, and which includes a main arrangement pattern provided along a closed curve and a plurality of sub-arrangement patterns, each of which has a smaller diameter than the main arrangement pattern; and a plurality of bobbins provided in the body and arranged along the closed curve, the string of conductive wire being wound around the plurality of bobbins along the closed curve to form the main arrangement pattern, the string of conductive wire being wound around each of the bobbins to form the sub-arrangement patterns.
    Type: Application
    Filed: December 5, 2012
    Publication date: April 30, 2015
    Applicant: NHK SPRING CO., LTD.
    Inventors: Masayuki Miura, Motoyuki Otsuka, Shuhei Okubo
  • Publication number: 20150069596
    Abstract: According to one embodiment, a semiconductor device includes a metal plate, a plurality of semiconductor chips, an insulation layer, a wiring layer, external connection terminals and a sealing resin portion. The metal plate includes a first surface and the plurality of semiconductor chips are laminated on a second surface of the metal plate. The insulation layer and the wiring layer are provided on the semiconductor chips. The external connection terminals are provided on the insulation layer and the wiring layer. The sealing resin portion seals the plurality of semiconductor chips while exposing the first surface of the metal plate. At least one pair of opposing outer peripheral surfaces of the metal plate are covered with the sealing resin portion.
    Type: Application
    Filed: February 26, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazushige KAWASAKI, Yoichiro KURITA, Satoshi TSUKIYAMA, Masayuki MIURA
  • Patent number: 8941246
    Abstract: In one embodiment, a semiconductor device includes a chip stacked body disposed on an interposer substrate and an interface chip mounted on the chip stacked body. The chip stacked body has plural semiconductor chips, and is electrically connected via through electrodes provided in the semiconductor chips excluding a lowermost semiconductor chip in a stacking order of the plural semiconductor chips and bump electrodes. The interface chip is electrically connected to the interposer substrate via a rewiring layer formed on a surface of an uppermost semiconductor chip in the stacking order or through electrodes provided in the interface chip.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Miura, Taku Kamoto, Takao Sato
  • Patent number: 8929742
    Abstract: An optical communication module in which the pin arrangement can be applied flexibly. An optical communication module has an outer shape formed based on normal standards and which is able to communicate with a host-side circuit board, etc. to which it is fitted, via a predetermined communication interface; wherein the optical communication module exchanges input/output I/F information with the circuit board, etc., and the communication interface can be switched to another communication interface based on these input/output I/F information.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: January 6, 2015
    Assignee: Furukawa Electric Co., Ltd.
    Inventor: Masayuki Miura
  • Publication number: 20140198633
    Abstract: A communication system that performs communication route control includes a center node and at least one node connected thereto via a communication line. The node includes an error-detecting unit that detects an error in the communication route, a route request packet transmitting unit that broadcasts a new route request packet in response to the detection, a route answer packet receiving unit that receives a route answer packet transmitted from a node that is a target node or a node having a valid route to the target node or from the center node, and a communication route updating unit that updates a communication route based on the route answer packet. A node that is the target node or the node having a valid route to the target node or the center node transmits a route answer packet to the node in response to a route request packet transmitted from the node.
    Type: Application
    Filed: July 12, 2012
    Publication date: July 17, 2014
    Inventors: Atsushi Kumagai, Masayuki Miura, Kunio Odaka, Kazutaka Shimoosako