Abstract: A current source apparatus includes a first MOS transistor having a drain serving as current input terminals with the gate connected to the drain, a first switch connected to the source of the first MOS transistor, a second MOS transistor having a drain serving as a current output terminal, a second switch connected to the source of the second MOS transistor, a third switch having one end connected to the gate of the first MOS transistor, and the other end connected to the gate of the second MOS transistor, and a drive circuit which controls the second switch and the third switch.

Abstract: There is provided a current source circuit in which a outflow current of an output terminal is equal to an inflow current thereof. The current source circuit includes a first transistor group converting a reference current from a reference current source into a voltage and a first transistor having a current mirror relationship with the first transistor group, and allowing an output current to flow therethrough. An error amplifier compares a voltage generated in the first transistor group and supplied to one input terminal with a voltage supplied to the other input terminal. A second transistor is driven with an output voltage of the error amplifier. A third transistor is driven with the output voltage of the error amplifier, and allows an output current to flow therethrough in a direction opposite to the output current of the first transistor with respect to an output terminal.

Abstract: Fixed pattern noise of an analog memory is reduced. Transfer paths of an address selection signal (SL) between an address generation unit (10) and respective storage elements (21) for storing an analog signal are constructed to have a substantially uniform electric characteristic in driving the storage elements (21) by the address selection signal (SL) to such an extent that the output signal of the analog memory is free from fixed pattern noise. A buffer unit (50) for temporarily storing and outputting the address selection signal is provided between the address generation unit (10) and the respective storage elements (21), and the buffer unit (50) is constructed to have an output characteristic substantially uniform between the storage elements (21). Also, lines between the buffer unit (50) and the storage elements (21) are constructed to have substantially the same electric characteristic.

Abstract: A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated.

Abstract: A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated.

Abstract: A comb filter easily implementable as a monolithic LSI without using a large-capacitance capacitor is provided. A comb-like frequency characteristic is realized by two delay circuits for delaying a signal for mutually different amounts of time and an operation circuit for deriving a sum or difference of the outputs thereof. An input select switch selectively outputs, instead of an image signal, a test signal, which is a DC signal having a predetermined amplitude, during a blanking interval of the image signal. A detector controls the gain of a variable-gain amplifier, provided for the output of either one of the delay circuits, in accordance with a difference between the output signal of the comb filter in response to the test signal and a predetermined reference signal. That is to say, the gain of the comb filter is controlled by using a stable test signal as a control signal, instead of a burst signal contained in an unstable image signal.