Patents by Inventor Masayuki Sasaki
Masayuki Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6640429Abstract: A multi-layer circuit board comprises: an insulating layer having upper and lower surfaces thereof, and wiring patterns arranged on the upper and lower surfaces of the insulating layer. A ferroelectric layer has a dielectric constant larger than that of the insulating layer and has upper and lower surfaces. The ferroelectric layer is arranged in the insulating layer in such a manner that the upper and lower surfaces of the ferroelectric layer coincide with the upper and lower surfaces of the insulating layer, respectively. A pair of electrode films are formed on the upper and lower surfaces of the ferroelectric layer, respectively, to define a capacitor incorporated in the multi-layer circuit board.Type: GrantFiled: February 12, 2002Date of Patent: November 4, 2003Assignee: Shinko Electric Industries Co., Ltd.Inventor: Masayuki Sasaki
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Patent number: 6604399Abstract: The present invention aims at providing a blade for use with a development device, method of manufacturing the same, die for manufacturing the same, and development device and image-forming device having the same that can more stably form a high quality image. The inventive blade is manufactured using a stamping die comprising an upper mold portion including a knockout, a lower mold portion including a punch and movable relative to the upper mold portion. In the stamping die, the knockout includes in cross section a first flat portion and a triangular projection portion that projects from the first flat portion, while the punch includes in cross section a second flat portion and a triangular groove portion formed on the second flat portion, and a first angle at which the triangular projection portion projects from the first flat portion is larger than a second angle at which the triangular groove portion is recessed from the second flat portion.Type: GrantFiled: October 24, 2000Date of Patent: August 12, 2003Assignee: Fujitsu LimitedInventors: Sadaaki Yoshida, Masayuki Sasaki, Keisuke Fujikura
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Patent number: 6603202Abstract: A circuit board for use in the production of semiconductor devices, in which the circuit board includes two or more by-pass capacitors formed thereon, and each by-pass capacitor is constituted from a first electrode layer formed in the uppermost layer of the circuit board, a ferroelectric layer formed, from a ferroelectric material having a higher dielectric constant than the upper electrode layer, over the first electrode layer, and a second electrode layer formed over the ferroelectric layer, and a semiconductor device comprising the circuit board having mounted thereon a semiconductor element. A circuit board-providing article for use in the production of the circuit board, and a process for the production of the circuit board and the semiconductor device, are also disclosed.Type: GrantFiled: December 22, 2000Date of Patent: August 5, 2003Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masayuki Sasaki, Hideaki Sakaguchi
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Patent number: 6597583Abstract: A multi-layer circuit board comprises: an insulating layer having upper and lower surfaces thereof, and wiring patterns arranged on the upper and lower surfaces of the insulating layer. A ferroelectric layer has a dieletric constant larger than that of the insulating layer and has upper and lower surfaces. The ferroelectric layer is arranged in the insulating layer in such a manner that the upper and lower surfaces of the ferroelectric layer coincide with the upper and lower surfaces of the insulating layer, respectively. A pair of electrode films are formed on the upper and lower surfaces of the ferroelectric layer, respectively, to define a capacitor incorporated in the multi-layer circuit board.Type: GrantFiled: October 17, 2000Date of Patent: July 22, 2003Assignee: Shinko Electric Industries Co., Ltd.Inventor: Masayuki Sasaki
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Publication number: 20030103471Abstract: The present invention as disclosed hereby is to provide a wireless base station by which it is possible to readily extend the wireless base station in the number thereof independently of the number of ports of the ATM transmission lines prepared on a wireless network control apparatus.Type: ApplicationFiled: December 3, 2002Publication date: June 5, 2003Applicant: Hitachi Kokusai Electric, Inc.Inventors: Osamu Watanabe, Shinji Ohnishi, Masayuki Sasaki
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Patent number: 6508544Abstract: An ink-jet head includes a head portion having a plurality of head segments and an ink feeding portion, where ink is supplied such that pipes each have one end connected to the head portion and the other end connected to one of ink feeding paths of the ink feeding portion. The pipes are held by elastic ring-shaped members that are further sidewise held by rigid ring-shaped members and vertically sandwiched between the ink feeding paths and an upper end portion of the head portion.Type: GrantFiled: July 18, 2000Date of Patent: January 21, 2003Assignee: Fujitsu LimitedInventors: Masayuki Sasaki, Hiromitsu Soneda, Koichi Sanpei, Mutsuo Watanabe, Takumi Kawamura
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Publication number: 20020195272Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.Type: ApplicationFiled: July 30, 2002Publication date: December 26, 2002Applicant: Shinko Electric Industries Co., Ltd.Inventors: Akio Rokugawa, Masayuki Sasaki, Yuichi Matsuda
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Patent number: 6498714Abstract: The present invention relates to a thin film capacitor device having a copper wiring layer, a dielectric layer, and a barrier layer interposed between the wiring layer and the dielectric layer. The barrier layer has the function of preventing diffusion of copper of the wiring layer. The thin film capacitor device may also include an insulating substrate, a planarizing layer, an adhesion layer, and an intermediate layer. The present invention may also relate to a printed circuit substrate having the described thin film capacitor device built therein as a capacitor.Type: GrantFiled: October 4, 2000Date of Patent: December 24, 2002Assignee: Shinko Electric Industries Co., Ltd.Inventors: Akira Fujisawa, Akihito Takano, Masayuki Sasaki
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Patent number: 6450623Abstract: The present invention has an object to provide an inkjet head and a method for manufacturing the inkjet head which not only protects a member at and/or near a surface onto which the nozzle plate is connected (nozzle connection surface), but also shortens the manufacturing time. A protective layer is provided between the nozzle plate and the piezo-electric element, enabling only the protective layer to be polished, protecting the piezo-electric element from being damaged by the polishing when the nozzle connection surface is formed. After the inkjet head is completed, the protective layer prevents ink leakage to the piezo-electric element.Type: GrantFiled: February 24, 1999Date of Patent: September 17, 2002Assignee: Fujitsu LimitedInventors: Mutsuo Watanabe, Masayuki Sasaki, Kouichi Sanpei, Mitsuhiro Soneda
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Patent number: 6441314Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.Type: GrantFiled: March 23, 2001Date of Patent: August 27, 2002Assignee: Shinko Electric Industries Co., Inc.Inventors: Akio Rokugawa, Masayuki Sasaki, Yuichi Matsuda
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Publication number: 20020115434Abstract: Maintenance of a wireless base station can be easily performed even when a wireless base station is installed on an electric pole. A maintenance terminal for communicating with a maintenance unit in the wireless base station through a wireless link is prepared for the wireless base station. The maintenance unit receives maintenance information and transmits the maintenance information received to the maintenance terminal, which is monitored by an operator. Also, the maintenance unit receives a control data from the maintenance terminal and controls a circuit operation of the wireless base station.Type: ApplicationFiled: October 4, 2001Publication date: August 22, 2002Inventors: Masayuki Sasaki, Shinji Ohnishi
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Patent number: 6418615Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.Type: GrantFiled: March 10, 2000Date of Patent: July 16, 2002Assignee: Shinko Electronics Industries, Co., Ltd.Inventors: Akio Rokugawa, Masayuki Sasaki, Yuichi Matsuda
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Publication number: 20020084104Abstract: A multi-layer circuit board comprises: an insulating layer having upper and lower surfaces thereof, and wiring patterns arranged on the upper and lower surfaces of the insulating layer. A ferroelectric layer has a dielectric constant larger than that of the insulating layer and has upper and lower surfaces. The ferroelectric layer is arranged in the insulating layer in such a manner that the upper and lower surfaces of the ferroelectric layer coincide with the upper and lower surfaces of the insulating layer, respectively. A pair of electrode films are formed on the upper and lower surfaces of the ferroelectric layer, respectively, to define a capacitor incorporated in the multi-layer circuit board.Type: ApplicationFiled: February 12, 2002Publication date: July 4, 2002Inventor: Masayuki Sasaki
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Patent number: 6410858Abstract: A multilayered wiring board comprising, at least, two wiring layers and an interlaminar insulating layer, in which said wiring board further has, incorporated therein, at least one capacitor element which comprises a sandwiched structure of a lower electrode-forming metallic layer having formed thereon at least one recess portion, a dielectric layer formed over the lower electrode-forming metallic layer, and an upper electrode-forming metallic layer formed over the dielectric layer, and its production process. The semiconductor device comprising the multilayered wiring board having mounted thereon a semiconductor element is also disclosed.Type: GrantFiled: December 14, 2000Date of Patent: June 25, 2002Assignee: Shinko Electric Industries Co. Ltd.Inventors: Masayuki Sasaki, Kazunari Imai
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Patent number: 6382780Abstract: The instant invention has an exemplified object to provide an inkjet head and recording device having such an inkjet head with a simpler structure as achieves higher quality of printing inexpensively than the conventional. The pressure-chamber plate of this invention is slit or divided into a plurality of elements.Type: GrantFiled: October 26, 1999Date of Patent: May 7, 2002Assignee: Fujitsu LimitedInventors: Mutsuo Watanabe, Masayuki Sasaki, Kouichi Sanpei, Hiromitsu Soneda, Akihiko Miyaki, Akira Iwaishi, Masahiro Ono, Takumi Kawamura, Tomoyuki Akahoshi
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Publication number: 20020043399Abstract: A multilayered wiring board comprising, at least, two wiring layers and an interlaminar insulating layer, in which said wiring board further has, incorporated therein, at least one capacitor element which comprises a sandwiched structure of a lower electrode-forming metallic layer having formed thereon at least one recess portion, a dielectric layer formed over the lower electrode-forming metallic layer, and an upper electrode-forming metallic layer formed over the dielectric layer, and its production process. The semiconductor device comprising the multilayered wiring board having mounted thereon a semiconductor element is also disclosed.Type: ApplicationFiled: December 14, 2000Publication date: April 18, 2002Inventors: Masayuki Sasaki, Kazunari Imai
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Publication number: 20020027892Abstract: The invention uses a CDMA base transceiver system that performs wireless communications through the use of a CDMA method. The invention thereby copes with a plurality of communication methods, through the use of that system, through an efficient construction thereof, simply by changing the software even if making no changes of, for example, the hardware. For example, an (illustrated) base band part is constructed using an FPGA 31 for processing a chip-rate signal through FPGA program data and a DSP 32 for processing a symbol-rate signal through DSP program data. Through the use of program data setting means (not illustrated) it is possible to change the FPGA program data used by the FPGA 31 and the DSP program data used by the DSP 32 to program data that corresponds to a different type of communication method.Type: ApplicationFiled: August 31, 2001Publication date: March 7, 2002Inventor: Masayuki Sasaki
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Patent number: 6341836Abstract: A water-repellent coating having a higher wiping resistance against a wiper and capable of being formed by a more simplified process than was previously possible. The method of forming the water-repellent coating comprises a flat hard body and a plating-processed fluoric polymer which are formed on a nozzle plate having a nozzle as a substrate around the nozzle.Type: GrantFiled: January 18, 2000Date of Patent: January 29, 2002Assignee: Fujitsu LimitedInventors: Shuji Koike, Masayuki Sasaki, Tomoyuki Akahoshi
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Patent number: 6328435Abstract: An ink jet head including a piezoelectric element having a displacing portion, a pressure chamber plate bonded to the piezoelectric element for defining a common ink chamber and a plurality of pressure chambers in cooperation with the piezoelectric element, and a nozzle plate bonded to the piezoelectric element and the pressure chamber plate and having a plurality of nozzles respectively communicating with the plurality of pressure chambers. Each pressure chamber is connected to the common ink chamber through a plurality of ink supply channels each having a substantially square cross-section.Type: GrantFiled: March 26, 1999Date of Patent: December 11, 2001Assignee: Fujitsu, Ltd.Inventors: Masahiro Ono, Masayuki Sasaki, Akihiko Miyaki, Akira Iwaishi, Takumi Kawamura
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Patent number: 6328434Abstract: It is an exemplified object of the present invention to provide an inkjet head, its manufacturing method, and a recording device that can form a high-quality image while preventing an ink leakage. To accomplish the object, an indent is provided at a joint surface of a pressure chamber plate with an adhesive.Type: GrantFiled: April 11, 2000Date of Patent: December 11, 2001Assignee: Fujitsu LimitedInventors: Hiromitsu Soneda, Masayuki Sasaki, Kouichi Sanpei, Mutsuo Watanabe