Patents by Inventor Massoud Tohidian
Massoud Tohidian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10749503Abstract: A discrete time filter network with an input signal connection and an output signal connection and comprising a capacitor bank with a plurality of history capacitors, and at least one sampling capacitor which operates at a predetermined cycling rate to couple to at least one history capacitor at a time, which history capacitor is selected from the capacitor bank so as to share electrical charge between such selected history capacitor and the sampling capacitor, wherein there is a plurality of sampling capacitors that are provided in the capacitor bank, and the discrete time filter network is provided with at least one switch network comprising a plurality of clock driven switches for making selected cyclical connections between the sampling capacitors and the history capacitors in the capacitor bank at the predetermined cycling rate.Type: GrantFiled: January 3, 2019Date of Patent: August 18, 2020Assignee: QUALINX B.V.Inventors: Iman Madadi, Massoud Tohidian, Seyed Amir Reza Ahmadi Mehr
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Publication number: 20190140610Abstract: A discrete time filter network with an input signal connection and an output signal connection and comprising a capacitor bank with a plurality of history capacitors, and at least one sampling capacitor which operates at a predetermined cycling rate to couple to at least one history capacitor at a time, which history capacitor is selected from the capacitor bank so as to share electrical charge between such selected history capacitor and the sampling capacitor, wherein there is a plurality of sampling capacitors that are provided in the capacitor bank, and the discrete time filter network is provided with at least one switch network comprising a plurality of clock driven switches for making selected cyclical connections between the sampling capacitors and the history capacitors in the capacitor bank at the predetermined cycling rate.Type: ApplicationFiled: January 3, 2019Publication date: May 9, 2019Inventors: Iman Madadi, Massoud Tohidian, Seyed Amir Reza Ahmadi Mehr
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Patent number: 10056881Abstract: A charge sharing filter includes a rotating capacitor, and a plurality of elementary filters, each elementary filter comprising: an elementary switch coupled between a first node of the respective elementary filter and a second node of the respective elementary filter; and a history capacitor coupled to the first node of the respective elementary filter, wherein the second nodes of the plurality of elementary filters are interconnected with the rotating capacitor in one interconnecting node.Type: GrantFiled: February 27, 2017Date of Patent: August 21, 2018Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski
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Publication number: 20170170810Abstract: A charge sharing filter includes a rotating capacitor, and a plurality of elementary filters, each elementary filter comprising: an elementary switch coupled between a first node of the respective elementary filter and a second node of the respective elementary filter; and a history capacitor coupled to the first node of the respective elementary filter, wherein the second nodes of the plurality of elementary filters are interconnected with the rotating capacitor in one interconnecting node.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Inventors: Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski
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Patent number: 9641164Abstract: A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks. Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on.Type: GrantFiled: November 19, 2014Date of Patent: May 2, 2017Assignee: Technische Universiteit DelftInventors: Massoud Tohidian, Robert Bogdan Staszewski, Ali Fotowat Ahmady, Seyed Amir Reza Ahmadi Mehr, Mahmoud Kamarei, Fabien Ndagijimana
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Publication number: 20170104455Abstract: A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks. Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Applicant: Technische Universiteit DelftInventors: Massoud Tohidian, Robert Bogdan Staszewski, Ali Fotowat Ahmady, Seyed Amir Reza Ahmadi Mehr, Mahmoud Kamarei, Fabien Ndagijimana
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Publication number: 20150372665Abstract: A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on.Type: ApplicationFiled: November 19, 2014Publication date: December 24, 2015Applicant: Technische Universiteit DelftInventors: Massoud Tohidian, Robert Bogdan Staszewski, Ali Fotowat Ahmady, Seyed Amir Reza Ahmadi Mehr, Mahmoud Kamarei, Fabien Ndagijimana
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Patent number: 9148125Abstract: A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low-pass filter is presented. The filter utilizes capacitors and a gm-cell, rather than operational amplifiers, and is thus compatible with digital nanoscale technology. A 7th-order charge-sampling and 6th-order voltage-sampling discrete time filter is disclosed. The order of the filter is easily extendable to higher orders. The charge rotating filter is process-scalable with Moore's law and amenable to digital nanoscale CMOS technology. Bandwidth of this filter is precise and robust to PVT variation. The filter exhibits very low power consumption per filter pole, low input-referred noise, wide tuning range, excellent linearity and low area per minimum bandwidth and filter pole.Type: GrantFiled: September 27, 2013Date of Patent: September 29, 2015Assignee: Technische Universiteit DelftInventors: Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski
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Publication number: 20150214926Abstract: A discrete-time filter for filtering an input signal comprises a switched capacitor network, the switched capacitor network comprising an input and an output, a number of switched capacitor paths arranged in parallel between the input and the output, each switched capacitor path comprising a capacitor, and a switch circuitry for switching each capacitor at a different time instant for outputting a filtered input signal.Type: ApplicationFiled: December 19, 2014Publication date: July 30, 2015Inventors: Massoud TOHIDIAN, Iman MADADI, Robert Bogdan STASZEWSKI
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Patent number: 9014653Abstract: A novel and useful reconfigurable superheterodyne receiver that employs a 3rd order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st order feedback based RF BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz to 1.2 GHz with a varying high IF range of 33 to 80 MHz. The gain stages are inverter based gm stages and the total gain of the receiver is 35 dB and in-band IIP3 at mid gain is +10 dBm. The NF of the receiver is 6.7 dB which is acceptable for the receiver without an LNA. The architecture is highly reconfigurable and follows the technology scaling.Type: GrantFiled: September 16, 2013Date of Patent: April 21, 2015Assignee: Technische Universiteit DelftInventors: Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski
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Publication number: 20140194081Abstract: The invention relates to a superheterodyne receiver, comprising: a sampling mixer being configured to sample an analog radio frequency signal using a certain sampling rate (fs) to obtain a discrete-time sampled signal, and to shift the discrete-time sampled signal towards a first intermediate frequency (|fRF?fLO|) to obtain an intermediate discrete-time signal sampled at the fs; a discrete-time filter being configured to filter the intermediate discrete-time signal at the fs to obtain a filtered signal; and a discrete-time mixer being configured to shift the filtered signal towards a second intermediate frequency (fIF).Type: ApplicationFiled: December 31, 2013Publication date: July 10, 2014Applicant: Huawei Technologies Co., Ltd.Inventors: Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski
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Publication number: 20140171009Abstract: A radio frequency receiver for receiving an analog radio frequency signal, the radio frequency receiver comprising a sampling mixer being configured to sample the analog radio frequency signal using a predetermined sampling rate (fs) to obtain a discrete-time signal, and to shift the discrete-time signal towards an intermediate frequency to obtain an intermediate discrete-time signal sampled at the predetermined sampling rate (fs), and a processing circuit for discrete-time processing the intermediate discrete-time signal at the predetermined sampling rate (fs).Type: ApplicationFiled: December 31, 2013Publication date: June 19, 2014Applicant: Huawei Technologies Co., Ltd.Inventors: Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski
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Publication number: 20140080436Abstract: A novel and useful reconfigurable superheterodyne receiver that employs a 3rd order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st order feedback based RF BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz to 1.2 GHz with varying high IF range of 33 to 80 MHz. The gain stages are inverter based gm stages and the total gain of the receiver is 35 dB and in-band IIP3 at mid gain is +10 dBm. The NF of the receiver is 6.7 dB which is acceptable for the receiver without an LNA. The architecture is highly reconfigurable and follows the technology scaling.Type: ApplicationFiled: September 16, 2013Publication date: March 20, 2014Applicant: Technische Universiteit DelftInventors: Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski