Abstract: Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another.

Abstract: Front facing piggyback wafer assembly. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. The plurality of integrated circuit devices are singulated to form individual integrated circuit devices. The carrier wafer may be processed to form integrated circuit structures prior to the attaching.

Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

Abstract: Inverted optical device. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. A flip wafer is attached to the plurality of light emitting diodes, away from the carrier wafer and the carrier wafer is removed. The plurality of light emitting diodes may be singulated to form individual light emitting diode devices.

Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Abstract: A microelectronic package includes a mounting structure, a microelectronic element associated with the mounting structure, and a plurality of conductive posts physically connected to the mounting structure and electrically connected to the microelectronic element. The conductive posts project from the mounting structure in an upward direction, at least one of the conductive posts being an offset post. Each offset post has a base connected to the mounting structure, the base of each offset post defining a centroid. Each offset post also defines an upper extremity having a centroid, the centroid of the upper extremity being offset from the centroid of the base in a horizontal offset direction transverse to the upward direction. The mounting structure is adapted to permit tilting of each offset post about a horizontal axis so that the upper extremities may wipe across a contact pad of an opposing circuit board.

Abstract: A three-dimensional grid array interposer includes first and second arrays of electrical terminals arranged in grid-like patterns having grid pitches of (X1,Y1) and (X2,Y2), where each electrical terminal of the first array corresponds to an electrical terminal of the second array, forming a corresponding pair of electrical terminals. The interposer also includes a plurality of stacked substrates, each substrate having a first surface, a second surface, a first edge, and a second edge, with each substrate having a row of electrical terminals of the first array along the first surface at the first edge and a row of electrical terminals of the second array along the first surface at its second edge, with a trace running along the first surface between each electrical terminal of each corresponding pair of electrical terminals. Spacers can be used to provide desired space transformation.

Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Abstract: A microelectronic connection component includes a substrate having a first surface, a second surface and a peripheral edge. First and second terminals are exposed at the first surface of the substrate. Wire bond pads are exposed proximate the peripheral edge of the substrate at the first surface. First conductive paths couple the first terminals to the wire bond pads. Bonding leads extend beyond the peripheral edge of the substrate. Second conductive paths couple the second terminals to the bonding leads.

Abstract: A method of expanding the contact pitch for un-diced chips in an array by pre-slicing the array in a first direction, attaching a lead frame to the chips' contacts, and then slicing the array and attached lead frame in the second direction. The lead frame has leads mechanically connected one another such that slicing the frame in the second direction along the mechanical connections separates the leads. Each lead has a first terminal which is conductively attached to a chip contact and a second terminal extending beyond the boundaries of the chip to which the first terminal is attached. In this manner, the contact pitch is effectively expanded to the terminal pitch of the leads.

Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Abstract: A multi-layer electronic package having polymeric tape layers, where at least one of the polymeric tape layers has a via, through hole, or aperture therein to pass wiring between the layers. This enables a balance of package size, adhesive thickness, chip access, inventory management, package width, JEDEC ball out, and die exposure. The polymeric tape layers have surface circuits (e.g., leads, pads, and wiring) located on the surface.

Abstract: A plurality of microelectronic assemblies are made by severing an in-process unit including an upper substrate and lower substrate with microelectronic elements disposed between the substrates. In a further embodiment, a lead frame is joined to a substrate so that the leads project from this substrate. Lead frame is joined to a further substrate with one or more microelectronic elements disposed between the substrates.

Abstract: A connection component for mounting a chip or other microelectronic element is formed from a starting unit including posts projecting from a dielectric element by crushing or otherwise reducing the height of at least some of the posts.

Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Abstract: Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate is included having opposing surfaces and a plurality of holes extending through the surfaces. Also included is a plurality of electrically conductive posts. Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts may be provided having tips in corresponding holes of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.

Abstract: A microelectronic unit has a structure including a microelectronic element such as a semiconductor chip with a first contact disposed remote from the periphery of the structure. The unit further includes first and second redistribution conductive pads disposed near a periphery of the structure and a conductive path incorporating first and second conductors extending toward the first contact, these conductors being connected to one another adjacent the first contact. The conductive path is connected to the first contact, and can provide signal routing from the periphery of the unit to the contact without the need for long stubs. A package may include a plurality of such units, which may be stacked on one another with the redistribution conductive pads of the various units connected to one another.

Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Abstract: A microelectronic assembly includes a microelectronic package having a microelectronic element with faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. The package includes a plurality of support elements disposed between the microelectronic element and the substrate and supporting the flexible substrate over the microelectronic element. At least some of the conductive posts are offset from the support elements. The assembly includes a circuitized substrate having conductive pads confronting the conductive posts of the microelectronic package, whereby the conductive posts are electrically interconnected with the conductive pads.

Abstract: A plurality of microelectronic assemblies (60) are made by severing an in-process unit including an upper substrate (40) and lower substrate (20) with microelectronic elements (36) disposed between the substrates. In a further embodiment, a lead frame (452) is joined to a substrate (440) so that the leads project from this substrate. Lead frame (452) is joined to a further substrate (470) with one or more microelectronic elements (436, 404, 406) disposed between the substrates.