Patents by Inventor Masum Hossain
Masum Hossain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876652Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.Type: GrantFiled: August 12, 2021Date of Patent: January 16, 2024Assignee: Rambus Inc.Inventors: Masum Hossain, Maruf H. Mohammad
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Patent number: 11838153Abstract: A digital signal processor includes analog to digital converters to convert an analog voltage to digital voltage in unit intervals of an analog signal. A decision feedback equalizer (DFE) determines a first level of a digital sum of a digital voltage in a first UI and digital voltages of adjacent UIs (taps). The DFE identifies predetermined sequences of levels of consecutive UIs that include the first level and selects one of the predetermined sequences to decode digital data encoded in the analog signal in the UI. The DSP may be programmable to include taps from UIs that may affect the first UI. The predetermined sequences may include levels of the digital sums of consecutive UIs of the analog signal. The predetermined sequences may be identified in a look-up table based on the first level.Type: GrantFiled: June 29, 2022Date of Patent: December 5, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Md Masum Hossain, Charles Boecker, Michael Raymond Trombley, Simon S. Li, Shaishav A. Desai
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Patent number: 11811379Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.Type: GrantFiled: December 22, 2021Date of Patent: November 7, 2023Assignee: Rambus Inc.Inventors: Masum Hossain, Carl W. Werner
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Publication number: 20230353177Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.Type: ApplicationFiled: May 8, 2023Publication date: November 2, 2023Inventors: Masum HOSSAIN, Nhat NGUYEN, Yikui Jen DONG, Arash ZARGARAN-YAZD, Wendemagegnehu BEYENE
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Patent number: 11792057Abstract: A communication system comprises a transmitter and a receiver that communicate differential phase modulated data over a wireline channel pair. The transmitter encodes data symbols by generating first and second data signals with differentially phase shifted signal transitions with respect to one another. The receiver receives the first data signal and the second data signal and samples the first data signal based on a signal transition timing of the second data signal to generate a first output data symbol. The receiver furthermore samples the second data signal based on signal transition timing of the first data signal to generate a second output data symbol.Type: GrantFiled: June 29, 2022Date of Patent: October 17, 2023Assignee: Rambus Inc.Inventors: Masum Hossain, Richelle L. Smith, Carl W. Werner
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Patent number: 11770275Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.Type: GrantFiled: June 28, 2022Date of Patent: September 26, 2023Assignee: Rambus Inc.Inventors: Masum Hossain, Nhat Nguyen, Charles Walter Boecker
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Publication number: 20230253974Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: ApplicationFiled: January 3, 2023Publication date: August 10, 2023Inventors: Masum HOSSAIN, Kenneth C. DYER, Nhat NGUYEN, Shankar TANGIRALA
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Patent number: 11706060Abstract: A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.Type: GrantFiled: August 30, 2021Date of Patent: July 18, 2023Assignee: Rambus Inc.Inventors: Haidang Lin, Charles Walter Boecker, Masum Hossain
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Patent number: 11683057Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.Type: GrantFiled: November 16, 2021Date of Patent: June 20, 2023Assignee: Rambus Inc.Inventors: Masum Hossain, Nhat Nguyen, Yikui Jen Dong, Arash Zargaran-Yazd, Wendemagegnehu Beyene
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Patent number: 11683206Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.Type: GrantFiled: May 18, 2021Date of Patent: June 20, 2023Assignee: Rambus Inc.Inventors: Masum Hossain, Nhat Nguyen, Charles Walter Boecker
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Patent number: 11575386Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: GrantFiled: May 10, 2021Date of Patent: February 7, 2023Assignee: Rambus Inc.Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
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Publication number: 20220417067Abstract: A communication system comprises a transmitter and a receiver that communicate differential phase modulated data over a wireline channel pair. The transmitter encodes data symbols by generating first and second data signals with differentially phase shifted signal transitions with respect to one another. The receiver receives the first data signal and the second data signal and samples the first data signal based on a signal transition timing of the second data signal to generate a first output data symbol. The receiver furthermore samples the second data signal based on signal transition timing of the first data signal to generate a second output data symbol.Type: ApplicationFiled: June 29, 2022Publication date: December 29, 2022Inventors: Masum Hossain, Richelle L. Smith, Carl W. Werner
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Publication number: 20220407749Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.Type: ApplicationFiled: June 28, 2022Publication date: December 22, 2022Inventors: Masum Hossain, Nhat Nguyen, Charles Walter Boecker
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Patent number: 11463283Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.Type: GrantFiled: October 19, 2020Date of Patent: October 4, 2022Assignee: Rambus Inc.Inventors: Masum Hossain, Jared L. Zerbe
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Patent number: 11411787Abstract: A communication system comprises a transmitter and a receiver that communicate differential phase modulated data over a wireline channel pair. The transmitter encodes data symbols by generating first and second data signals with differentially phase shifted signal transitions with respect to one another. The receiver receives the first data signal and the second data signal and samples the first data signal based on a signal transition timing of the second data signal to generate a first output data symbol. The receiver furthermore samples the second data signal based on signal transition timing of the first data signal to generate a second output data symbol.Type: GrantFiled: June 30, 2021Date of Patent: August 9, 2022Assignee: Rambus Inc.Inventors: Masum Hossain, Richelle L. Smith, Carl W. Werner
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Patent number: 11405242Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (IS I) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of IS I offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the IS I offset for the immediate symbol.Type: GrantFiled: June 14, 2019Date of Patent: August 2, 2022Assignee: Rambus Inc.Inventors: Masum Hossain, Nhat Nguyen, Charles Walter Boecker
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Publication number: 20220190808Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.Type: ApplicationFiled: December 22, 2021Publication date: June 16, 2022Inventors: Masum HOSSAIN, Carl W. WERNER
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Publication number: 20220149876Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.Type: ApplicationFiled: November 16, 2021Publication date: May 12, 2022Inventors: Masum HOSSAIN, Nhat NGUYEN, Yikui Jen DONG, Arash ZARGARAN-YAZD, Wendemagegnehu BEYENE
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Publication number: 20220103404Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.Type: ApplicationFiled: August 12, 2021Publication date: March 31, 2022Applicant: Rambus Inc.Inventors: Masum Hossain, Maruf H. Mohammad
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Publication number: 20220045885Abstract: A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.Type: ApplicationFiled: August 30, 2021Publication date: February 10, 2022Inventors: Haidang Lin, Charles Walter Boecker, Masum Hossain