Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

Abstract: Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.

Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

Abstract: A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.

Abstract: Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.

Abstract: Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.

Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

Abstract: Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.