Abstract: An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus as a slave node. The device comprises a transceiver configured to: generate a first signal by delaying an inverted signal of a transmission data signal: generate a second signal based on the transmission data signal, where the second signal has a low slew rate: selectively output the first signal or the second signal as a third signal, in response to a selector signal: and generate a clock signal in response to the third signal, where the clock signal is at a high level when the third signal is at a low level, and where the clock signal is at the low level when the third signal is at the high level.

Abstract: An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus as a slave node. The device comprises a transceiver configured to: generate a first signal by delaying an inverted signal of a transmission data signal; generate a second signal based on the transmission data signal, where the second signal has a low slew rate; selectively output the first signal or the second signal as a third signal, in response to a selector signal; and generate a clock signal in response to the third signal, where the clock signal is at a high level when the third signal is at a low level, and where the clock signal is at the low level when the third signal is at the high level.

Abstract: In an example embodiment, a communication system provides a clock extension peripheral interface (CXPI) communication bus that is coupled to a master node and a plurality of slave nodes. The master node is configured to transmit a reference clock signal on the CXPI communication bus. Each slave node of the plurality of slave nodes is configured to receive the reference clock signal from the CXPI communication bus and to transmit and receive data to and from the CXPI communication bus based on the reference clock signal.

Abstract: In an example embodiment, a communication system provides a clock extension peripheral interface (CXPI) communication bus that is coupled to a master node and a plurality of slave nodes. The master node is configured to transmit a reference clock signal on the CXPI communication bus. Each slave node of the plurality of slave nodes is configured to receive the reference clock signal from the CXPI communication bus and to transmit and receive data to and from the CXPI communication bus based on the reference clock signal.

Abstract: An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus as a slave node. The device comprises a transceiver configured to: generate a first signal by delaying an inverted signal of a transmission data signal; generate a second signal based on the transmission data signal, where the second signal has a low slew rate; selectively output the first signal or the second signal as a third signal, in response to a selector signal; and generate a clock signal in response to the third signal, where the clock signal is at a high level when the third signal is at a low level, and where the clock signal is at the low level when the third signal is at the high level.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus. The device comprises a transceiver configured to: detect a baud rate clock signal and a phase difference between the baud rate clock signal and an input data signal that was generated asynchronously from the baud rate clock signal; obtain a timing from an edge of the baud rate clock signal based the phase difference; capture a value of the input data signal at the timing; and transmit the captured value as an output data signal over the CXPI bus.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus. The device comprises a transceiver configured to: detect a baud rate clock signal and a phase difference between the baud rate clock signal and an input data signal that was generated asynchronously from the baud rate clock signal; obtain a timing from an edge of the baud rate clock signal based the phase difference; capture a value of the input data signal at the timing; and transmit the captured value as an output data signal over the CXPI bus.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.

Abstract: An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.

Abstract: A method for designing power supply wiring of a semiconductor integrated circuit having a logic circuit. A first power consumption value of the logic circuit is calculated based on logic connection information, and the power supply wiring is laid out in accordance with the first power consumption value. Logic modification connection information relating to the modified logic circuit is generated when the logic circuit is modified after the power supply wiring is laid out. A second power consumption value of the modified logic circuit is calculated based on the logic modification connection information. When the second power consumption value exceeds the first power consumption value, it is determined that the power supply wiring must be re-laid out. It is thus easily determined whether to re-lay out the power supply wiring without performing power supply network analysis.

Abstract: In a higher layer, power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. Then, a resistor network of the power source wiring within the logic-undecided functional block is prepared by assuming that a current source has been connected to a power source terminal of the logic-undecided functional block. A resistor network of a total power source wiring in the higher layer is prepared by using this local resistor network. An optimum width of the power source wiring is determined by analyzing this resistor network. Based on the width, the power source wiring of the higher layer is rewired.