Abstract: A method for designing power supply wiring of a semiconductor integrated circuit having a logic circuit. A first power consumption value of the logic circuit is calculated based on logic connection information, and the power supply wiring is laid out in accordance with the first power consumption value. Logic modification connection information relating to the modified logic circuit is generated when the logic circuit is modified after the power supply wiring is laid out. A second power consumption value of the modified logic circuit is calculated based on the logic modification connection information. When the second power consumption value exceeds the first power consumption value, it is determined that the power supply wiring must be re-laid out. It is thus easily determined whether to re-lay out the power supply wiring without performing power supply network analysis.

Abstract: A method for designing a semiconductor device having a plurality of logic elements provided with a plurality of power supplies. First, a power supply type name is given to each power supply in accordance with the purpose of the power supply in each logic element. Each logic element is associated with the power supply type name of the power supply that is to be provided to the logic element. A power supply group is formed for each power supply. Specific information of each power supply group associating the power supply type name with supplied voltage is generated. Then, the power supply provided to each logic element is determined by allocating the power supply group to the logic element. The method simplifies designing the layout of a semiconductor device operated by multiple power supplies.

Abstract: In a higher layer, power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. Then, a resistor network of the power source wiring within the logic-undecided functional block is prepared by assuming that a current source has been connected to a power source terminal of the logic-undecided functional block. A resistor network of a total power source wiring in the higher layer is prepared by using this local resistor network. An optimum width of the power source wiring is determined by analyzing this resistor network. Based on the width, the power source wiring of the higher layer is rewired.

Abstract: A method for designing a semiconductor device having a plurality of logic elements provided with a plurality of power supplies. First, a power supply type name is given to each power supply in accordance with the purpose of the power supply in each logic element. Each logic element is associated with the power supply type name of the power supply that is to be provided to the logic element. A power supply group is formed for each power supply. Specific information of each power supply group associating the power supply type name with supplied voltage is generated. Then, the power supply provided to each logic element is determined by allocating the power supply group to the logic element. The method simplifies designing the layout of a semiconductor device operated by multiple power supplies.