Patents by Inventor Mathew Philip

Mathew Philip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210319423
    Abstract: A payment handling system may operate to handle payments for the cost of a transaction in which one or more devices operate in an offline mode. The payment handling system may allow for merchant devices to make modifications to local versions of an open ticket while in an off-line mode. When a merchant device subsequently enters an online mode, the systems and techniques may operate to reconcile differences between the local versions of the open ticket.
    Type: Application
    Filed: April 26, 2021
    Publication date: October 14, 2021
    Inventors: Christopher Philip Renke, Michael Wells White, Eric Dickeson Muller, Mathew Wilson
  • Publication number: 20210305089
    Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a first mandrel layer and a second mandrel layer on the dielectric layer and patterning the first mandrel layer and the second mandrel layer to form respective first and second patterns in the first and second mandrel layers. The first pattern includes a first line segment and a first wing segment. The first wing segment is filled with a first spacer material to form a first spacer. The method further includes removing exposed portions of the first and second mandrel layers, transferring an image of the first and second patterns, patterning the dielectric layer and depositing a metal into the patterned dielectric layer to form a metallic interconnect structure. The metallic interconnect structure includes first and second metallic lines with the second metallic line having a line break corresponding to the first spacer.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Timothy Mathew Philip, Somnath Ghosh, Robert Robison
  • Publication number: 20210305503
    Abstract: A method of forming a phase change memory device is provided. The method includes forming a spacer layer on a substrate, and forming a heater terminal contact in the spacer layer. The method further includes forming a liner layer on the heater terminal contact and the spacer layer, and forming a heater terminal in electrical contact with the heater terminal contact in the liner layer. The method further includes forming a conductive projection segment on the heater terminal. The method further includes forming a phase change material layer on the conductive projection segment, and forming a phase change material terminal on the phase change material layer, wherein an electrical current can pass between the heater terminal and the phase change material terminal through the phase change material layer.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Timothy Mathew Philip, Nicole Saulnier, Lawrence A. Clevenger
  • Publication number: 20210305505
    Abstract: A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Timothy Mathew Philip, Lawrence A. Clevenger, Kevin W. Brew
  • Patent number: 11133058
    Abstract: A multiterminal non-volatile memory cross-bar array system includes a set of conductive row rails, a set of conductive column rails configured to form a plurality of crosspoints at intersections between the conductive rails and the conductive column rails and a resistive processing unit at each of the crosspoints each representing a neuron in a neural network. At least one given conductive row rail includes first and second row lines is in contact with a given resistive processing unit. At least one given conductive column rail including first and second column lines is in contact with the given resistive processing unit.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Timothy Mathew Philip, Kevin W. Brew, Lawrence A. Clevenger
  • Publication number: 20210296169
    Abstract: A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer wails on the opposed vertical wails of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.
    Type: Application
    Filed: March 23, 2020
    Publication date: September 23, 2021
    Inventors: Timothy Mathew Philip, Sagarika Mukesh, Dominik Metzler, Ashim Dutta, John Christopher Arnold
  • Publication number: 20210288238
    Abstract: Devices, systems, and/or methods that can facilitate topological quantum computing are provided. According to an embodiment, a device can comprise a circuit layer formed on a wiring layer of the device and that comprises control components. The device can further comprise a topological qubit device formed on the circuit layer and that comprises a nanorod capable of hosting Majorana fermions and a quantum well tunable Josephson junction that is coupled to the control components.
    Type: Application
    Filed: March 16, 2020
    Publication date: September 16, 2021
    Inventors: Steven J. Holmes, Timothy Mathew Philip, Sagarika Mukesh, Youngseok Kim, Devendra K. Sadana, Robert Robison
  • Publication number: 20210280457
    Abstract: Embodiments of the present invention disclose a method and apparatus for making a multi-layer device comprising a conductive layer, a dielectric layer formed on top of conductive layer, a via pattern formed in the dielectric layer, wherein the via pattern is comprised of a plurality of channels and columns, wherein a first portion of the via pattern downwards extends through the entire dielectric layer to directly contact the conductive layer, wherein a second portion of the via pattern extends downwards without coming into direct contact with the conductive layer.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 9, 2021
    Inventors: Timothy Mathew Philip, Nicholas Anthony Lanzillo, Daniel James Dechene, Robert Robison
  • Publication number: 20210280465
    Abstract: Techniques for forming self-aligned subtractive top vias using a via hardmask supported by scaffolding are provided. In one aspect, a method of forming top vias includes: forming metal lines on a substrate using line hardmasks; patterning vias in the line hardmasks; filling the vias and trenches in between the metal lines with a via hardmask material to form via hardmasks and a scaffolding adjacent to and supporting the via hardmasks; removing the line hardmasks; and recessing the metal lines using the via hardmasks to form the top vias that are self-aligned with the metal lines. The scaffolding can also be placed prior to patterning of the vias in the line hardmasks. A structure formed in accordance with the present techniques containing top vias is also provided.
    Type: Application
    Filed: March 9, 2020
    Publication date: September 9, 2021
    Inventors: Sagarika Mukesh, Dominik METZLER, CHANRO PARK, Timothy Mathew Philip
  • Publication number: 20210265201
    Abstract: A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.
    Type: Application
    Filed: February 20, 2020
    Publication date: August 26, 2021
    Inventors: Timothy Mathew Philip, Daniel James Dechene, Somnath Ghosh, Robert Robison
  • Patent number: 11094590
    Abstract: Techniques for forming self-aligned subtractive top vias using a via hardmask supported by scaffolding are provided. In one aspect, a method of forming top vias includes: forming metal lines on a substrate using line hardmasks; patterning vias in the line hardmasks; filling the vias and trenches in between the metal lines with a via hardmask material to form via hardmasks and a scaffolding adjacent to and supporting the via hardmasks; removing the line hardmasks; and recessing the metal lines using the via hardmasks to form the top vias that are self-aligned with the metal lines. The scaffolding can also be placed prior to patterning of the vias in the line hardmasks. A structure formed in accordance with the present techniques containing top vias is also provided.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sagarika Mukesh, Dominik Metzler, Chanro Park, Timothy Mathew Philip
  • Publication number: 20210210379
    Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.
    Type: Application
    Filed: January 7, 2020
    Publication date: July 8, 2021
    Inventors: Daniel James Dechene, Timothy Mathew Philip, Somnath Ghosh, Robert Robison
  • Patent number: 10998193
    Abstract: Integrated chips and methods of forming the same include forming a first set of sidewall spacers on a first mandrel at first vertical level. The first mandrel is etched away. A second set of sidewall spacers is formed on a second mandrel at a second vertical level. A portion of the second set of sidewall spacers vertically overlaps with a portion of the first set of sidewall spacers. The second mandrel is etched away. A first hardmask layer is etched, using the vertically overlapping first set of sidewall spacers and second set of sidewall spacers as a mask.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Mathew Philip, Somnath Ghosh, Daniel James Dechene, Robert Robison, Lawrence A. Clevenger
  • Patent number: 10719301
    Abstract: Computer systems and associated methods are disclosed to implement a model development environment (MDE) that allows a team of users to perform iterative model experiments to develop machine learning (ML) media models. In embodiments, the MDE implements a media data management interface that allows users to annotate and manage training data for models. In embodiments, the MDE implements a model experimentation interface that allows users to configure and run model experiments, which include a training run and a test run of a model. In embodiments, the MDE implements a model diagnosis interface that displays the model's performance metrics and allows users to visually inspect media samples that were used during the model experiment to determine corrective actions to improve model performance for later iterations of experiments. In embodiments, the MDE allows different types of users to collaborate on a series of model experiments to build an optimal media model.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 21, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Sunny Dasgupta, Sri Kaushik Pavani, Shriram Venkataramana, Sabya Sachi, Himanshu Prafulla Shringarpure, Divya Varshney, FNU Najih, Suryansh Purwar, Niyaz Puzhikkunnath, Mathew Philip, Shubhangam Agrawal
  • Patent number: 10394299
    Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 27, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
  • Publication number: 20190076366
    Abstract: The present invention relates to an adhesive-free pharmaceutical composition for the treatment of hepatitis B virus infections, comprising at least one guanine-based antiviral active pharmaceutical ingredient. More specifically, the present invention concerns an oral pharmaceutical composition comprising: adhesive-free granules comprising therapeutically effective amount of entecavir and at least one intra-granular pharmaceutically acceptable excipient; at least one extra-granular pharmaceutical excipient, and, optionally, a moisture barrier coating. A method of manufacturing an adhesive-free pharmaceutical composition is also disclosed.
    Type: Application
    Filed: April 3, 2018
    Publication date: March 14, 2019
    Applicant: Pharmascience, Inc.
    Inventors: Mathew Philip, Naresh Talwar
  • Patent number: 9958918
    Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 1, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Satyanarayana Sahu, Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
  • Publication number: 20170336845
    Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.
    Type: Application
    Filed: May 23, 2016
    Publication date: November 23, 2017
    Inventors: Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
  • Publication number: 20170336840
    Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.
    Type: Application
    Filed: May 23, 2016
    Publication date: November 23, 2017
    Inventors: Satyanarayana Sahu, Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
  • Publication number: 20170014340
    Abstract: Orally disintegrating medicaments comprising Nabilone allow for improved treatment of nausea arising from chemo therapy for cancer. The medicaments comprise appropriate excipients such that the medicament disintegrates in the mouth in 30 seconds or less, while exhibiting sufficient stability for storage. In a preferred embodiment, the medicament is in the form of a tablet formed from granules. The granules consist of an intra-granular fraction comprising nabilone, mannitol, and polyvinyl pyrrolidone and an extra-granular fraction comprising mannitol, calcium silicate, crospovidone, and magnesium stearate. Processes for manufacturfing such medicaments are also disclosed.
    Type: Application
    Filed: March 4, 2015
    Publication date: January 19, 2017
    Applicant: Pharmascience Inc.
    Inventors: Ousmane Diallo, Mathew Philip, Naresh Talwar