Abstract: A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

Abstract: A multiterminal non-volatile memory cross-bar array system includes a set of conductive row rails, a set of conductive column rails configured to form a plurality of crosspoints at intersections between the conductive rails and the conductive column rails and a resistive processing unit at each of the crosspoints each representing a neuron in a neural network. At least one given conductive row rail includes first and second row lines is in contact with a given resistive processing unit. At least one given conductive column rail including first and second column lines is in contact with the given resistive processing unit.

Abstract: A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer wails on the opposed vertical wails of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.

Abstract: Devices, systems, and/or methods that can facilitate topological quantum computing are provided. According to an embodiment, a device can comprise a circuit layer formed on a wiring layer of the device and that comprises control components. The device can further comprise a topological qubit device formed on the circuit layer and that comprises a nanorod capable of hosting Majorana fermions and a quantum well tunable Josephson junction that is coupled to the control components.

Abstract: Embodiments of the present invention disclose a method and apparatus for making a multi-layer device comprising a conductive layer, a dielectric layer formed on top of conductive layer, a via pattern formed in the dielectric layer, wherein the via pattern is comprised of a plurality of channels and columns, wherein a first portion of the via pattern downwards extends through the entire dielectric layer to directly contact the conductive layer, wherein a second portion of the via pattern extends downwards without coming into direct contact with the conductive layer.

Abstract: Techniques for forming self-aligned subtractive top vias using a via hardmask supported by scaffolding are provided. In one aspect, a method of forming top vias includes: forming metal lines on a substrate using line hardmasks; patterning vias in the line hardmasks; filling the vias and trenches in between the metal lines with a via hardmask material to form via hardmasks and a scaffolding adjacent to and supporting the via hardmasks; removing the line hardmasks; and recessing the metal lines using the via hardmasks to form the top vias that are self-aligned with the metal lines. The scaffolding can also be placed prior to patterning of the vias in the line hardmasks. A structure formed in accordance with the present techniques containing top vias is also provided.

Abstract: A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

Abstract: Techniques for forming self-aligned subtractive top vias using a via hardmask supported by scaffolding are provided. In one aspect, a method of forming top vias includes: forming metal lines on a substrate using line hardmasks; patterning vias in the line hardmasks; filling the vias and trenches in between the metal lines with a via hardmask material to form via hardmasks and a scaffolding adjacent to and supporting the via hardmasks; removing the line hardmasks; and recessing the metal lines using the via hardmasks to form the top vias that are self-aligned with the metal lines. The scaffolding can also be placed prior to patterning of the vias in the line hardmasks. A structure formed in accordance with the present techniques containing top vias is also provided.

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.

Abstract: Integrated chips and methods of forming the same include forming a first set of sidewall spacers on a first mandrel at first vertical level. The first mandrel is etched away. A second set of sidewall spacers is formed on a second mandrel at a second vertical level. A portion of the second set of sidewall spacers vertically overlaps with a portion of the first set of sidewall spacers. The second mandrel is etched away. A first hardmask layer is etched, using the vertically overlapping first set of sidewall spacers and second set of sidewall spacers as a mask.

Abstract: Computer systems and associated methods are disclosed to implement a model development environment (MDE) that allows a team of users to perform iterative model experiments to develop machine learning (ML) media models. In embodiments, the MDE implements a media data management interface that allows users to annotate and manage training data for models. In embodiments, the MDE implements a model experimentation interface that allows users to configure and run model experiments, which include a training run and a test run of a model. In embodiments, the MDE implements a model diagnosis interface that displays the model's performance metrics and allows users to visually inspect media samples that were used during the model experiment to determine corrective actions to improve model performance for later iterations of experiments. In embodiments, the MDE allows different types of users to collaborate on a series of model experiments to build an optimal media model.

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

Abstract: The present invention relates to an adhesive-free pharmaceutical composition for the treatment of hepatitis B virus infections, comprising at least one guanine-based antiviral active pharmaceutical ingredient. More specifically, the present invention concerns an oral pharmaceutical composition comprising: adhesive-free granules comprising therapeutically effective amount of entecavir and at least one intra-granular pharmaceutically acceptable excipient; at least one extra-granular pharmaceutical excipient, and, optionally, a moisture barrier coating. A method of manufacturing an adhesive-free pharmaceutical composition is also disclosed.

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

Abstract: Orally disintegrating medicaments comprising Nabilone allow for improved treatment of nausea arising from chemo therapy for cancer. The medicaments comprise appropriate excipients such that the medicament disintegrates in the mouth in 30 seconds or less, while exhibiting sufficient stability for storage. In a preferred embodiment, the medicament is in the form of a tablet formed from granules. The granules consist of an intra-granular fraction comprising nabilone, mannitol, and polyvinyl pyrrolidone and an extra-granular fraction comprising mannitol, calcium silicate, crospovidone, and magnesium stearate. Processes for manufacturfing such medicaments are also disclosed.

Abstract: The present invention relates to an adhesive-free pharmaceutical composition for the treatment of hepatitis B virus infections, comprising at least one guanine-based antiviral active pharmaceutical ingredient. More specifically, the present invention concerns an oral pharmaceutical composition comprising: adhesive-free granules comprising therapeutically effective amount of entecavir and at least one intra-granular pharmaceutically acceptable excipient; at least one extra-granular pharmaceutical excipient, and, optionally, a moisture barrier coating. A method of manufacturing an adhesive-free pharmaceutical composition is also disclosed.

Abstract: The invention described herein utilizes devices under test (DUTs) outfitted with stored, predefined test sequences, testers equipped with vector-signal generation (VSG) and vector-signal analysis (VSA) functionality, and novel methods for combining loopback and single-ended test functions in order to obtain higher testing efficiency for DUTs using Bluetooth or other time-division duplex (TDD) based communications.

Abstract: System and method for facilitating testing of multiple data packet signal transceivers involving data-packet-signal replication and one or more status signals indicating successful and unsuccessful receptions of confirmation signals. Based upon the one or more status signals, one or more control signals cause the replicated data packet signals to be distributed to the devices under test (DUTs) such that, following successful and unsuccessful receptions of confirmation signals, corresponding replicated data packet signals are caused to fail to conform in part or to conform, respectively, with a predetermined data packet signal standard.