Abstract: A low-power quadrature generator is provided for accurately generating in-phase signals and quadrature signals.

Abstract: A charge pump is disclosed including an output capacitive element to store an output voltage, a charging current source to charge the output capacitive element, a charging switching element to couple a first bias voltage to the charging current source in response to a charging signal, a discharging current source to discharge the output capacitive element, a discharging switching element to couple a second bias voltage to the discharging current source in response to a discharging signal, a unity gain amplifier to generate an amplifier voltage substantially equal to the output voltage, a first switching element to couple the amplifier voltage to the charging current source in response to a leakage prevention signal; and a second switching element to couple the amplifier voltage to the discharging current source in response to the leakage prevention signal.

Abstract: RF voltage amplifier circuits which have high voltage amplifier gain and input signal frequency range, and a method for boosting the voltage amplifier gain and input signal frequency range in such circuits is provided. A method includes the steps of providing a voltage amplifier having a transistor with the grounded source and the drain connected to a power supply via a resistive load, and providing an integrated inductor for biasing the transistor, having an inductor connecting an input signal terminal to the gate of the transistor and a capacitor connecting the gate and the source of the transistor. The next step includes selecting a resonant frequency of the integrated inductor at a frequency where the voltage amplifier gain is starting to roll-off, for boosting the voltage amplifier gain and the input signal frequency range. The integrated inductor preferably operates at a resonant frequency approximately matching the roll-off frequency of the voltage amplifier.

Abstract: In a phase lock loop, a charge pump includes a current mirror circuit. The current mirror circuit contains a bias current source and a current mirror source which mirrors the current of the bias current source. The current mirror source is turned on and off in accordance with an output signal from a phase detector to produce correction signals for a VCO. To conserve power, circuits are provided for turning the bias current source on just before it is needed by the current mirror source and for turning the bias current source off just after the current mirror source turns off.

Abstract: A phase-locked loop includes a phase/frequency detector, a charge pump, a loop filter, an oscillator and a feedback circuit coupled between the oscillator and the phase/frequency detector. The loop filter includes a first temperature-variable well resistor and has a gain directly related to resistance of the first resistor. An oscillator coupled to the loop filter includes a voltage-to-current converter that generates a reference current based on the loop filter voltage, and a current-controlled oscillator that generates the output clock based on the value of the reference current. The voltage-to-current converter includes a first transistor that receives the loop filter voltage at a gate and a second temperature-variable well resistor coupled to the source of the first transistor. The oscillator gain is indirectly related to the resistance of the second resistor. The second well resistor and first well resistor have substantially equal resistances and substantially equal temperature coefficients.

Abstract: A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and second serially connected voltage-controlled delay elements that each introduce a time delay to produce a first delayed clock and the output clock. An S-R flip-flop receives the first delayed clock on its R-input and either the output clock or the reference clock on its S-input to produce a loop clock. The loop clock is provided to the first delay element. A multiplexer selects the reference clock as the S input to the flip-flop once every N cycles, and selects the output clock as the S input the remaining N−1 cycles. A phase detector, a charge pump and a loop filter compare the phase of the output clock to the phase of the reference clock and apply a voltage to the delay elements to correct any phase differences.

Abstract: A source-switched or gate-switched charge pump having a cascoded output. A first current-mirror comprised of p-channel CMOS transistors is coupled on one side of an output node and a second current mirror comprised of n-channel CMOS transistors is coupled on the opposite side of the output node. A reference current source is coupled between the current mirrors. A p-channel CMOS cascode transistor is coupled between the first current mirror and the output node, and an n-channel CMOS cascode transistor is coupled between the second current mirror and the output node. A p-channel CMOS transistor switch is coupled to either the source or the gate of the output transistor of the first current mirror and receives a first control signal at its gate. An n-channel CMOS transistor switch is coupled to either the source or the gate of the output transistor of the second current mirror and receives a second control signal at its gate.