Patents by Inventor Matthew A. Fisch

Matthew A. Fisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6668309
    Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: Derek T. Bachand, Paul Breuder, Matthew A. Fisch
  • Publication number: 20030115424
    Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.
    Type: Application
    Filed: January 29, 2003
    Publication date: June 19, 2003
    Inventors: Derek T. Bachand, Paul Breuder, Matthew A. Fisch
  • Patent number: 6578116
    Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: June 10, 2003
    Assignee: Intel Corporation
    Inventors: Derek T. Bachand, Paul Breuder, Matthew A. Fisch
  • Publication number: 20020199068
    Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.
    Type: Application
    Filed: August 9, 2002
    Publication date: December 26, 2002
    Inventors: Derek T. Bachand, Paul Breuder, Matthew A. Fisch
  • Patent number: 6460119
    Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: October 1, 2002
    Assignee: Intel Corporation
    Inventors: Derek T. Bachand, Paul Breuder, Matthew A. Fisch
  • Patent number: 6268749
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: July 31, 2001
    Assignee: Intel Corporation
    Inventors: Matthew A. Fisch, Chakrapani Pathikonda, Javed S. Barkatullah
  • Patent number: 6216208
    Abstract: A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: April 10, 2001
    Assignee: Intel Corporation
    Inventors: Robert Greiner, David L. Hill, Chinna Prudvi, Derek T. Bachand, Matthew A. Fisch
  • Patent number: 6208180
    Abstract: A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: March 27, 2001
    Assignee: Intel Corporation
    Inventors: Matthew A. Fisch, Chakrapani Pathikonda, Javed S. Barkatullah
  • Patent number: 6209068
    Abstract: A data control method in a microprocessor is disclosed. According to the method, a request is generated on an external bus for data to be read to the processor. The requested data is read from the external bus to an intermediate memory in the processor and, thereafter, read from the intermediate memory to a destination. When the intermediate memory is full, the read of data from the external bus is stalled until the intermediate memory is no longer full. Typically, stalling is accomplished by generating a stall signal on the external bus, which may be generated during a cache coherency phase of the transaction to which the requested data relates.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: March 27, 2001
    Assignee: Intel Corporation
    Inventors: David L. Hill, Chinna Prudvi, Derek T. Bachand, Matthew A. Fisch
  • Patent number: 6114887
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: September 5, 2000
    Assignee: Intel Corporation
    Inventors: Chakrapani Pathikonda, Matthew A. Fisch, Michael W. Rhodehamel
  • Patent number: 6078981
    Abstract: A livelock preventative measure is provided for agents in a multi-processor computing system. Livelock may occur when multiple agents each trade ownership of data in an attempt to modify it. When livelock occurs, a first agent posts a bus transaction for a data and, if a second agent posts a bus transaction for the same data, the first agent may stall the bus transaction of the second agent until the first agent has completed its operation on the data.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: June 20, 2000
    Assignee: Intel Corporation
    Inventors: David L. Hill, Chinna Prudvi, Derek T. Bachand, Paul Breuder, Matthew A. Fisch
  • Patent number: 6009477
    Abstract: Each of a plurality of device or agents connected to a computer system bus is provided with a mechanism for unilaterally and dynamically limiting the depth of a pipeline of the bus. Each agent includes a state machine which indicates whether the bus is in a throttled state, a stalled state or a free state. When in a free state, an agent having control of the bus may transmit any number of bus transactions and the depth of the pipeline may therefore increase. In the throttled state, the agent may transmit only a single bus transaction from the throttled state, the state machine always transitions either to the stalled state or to the free state. In the stalled state, no agents may transmit transactions onto the bus and the depth of the pipeline therefore cannot increase and instead may decrease with time as previously issued transactions are drained from the bus.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: December 28, 1999
    Assignee: Intel Corporation
    Inventors: Nitin Sarangdhar, Michael Rhodehamel, Matthew Fisch
  • Patent number: 6006299
    Abstract: In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: December 21, 1999
    Assignee: Intel Corporation
    Inventors: Wen-Hann Wang, Konrad K. Lai, Gurbir Singh, Mandar S. Joshi, Nitin V. Sarangdhar, Matthew A. Fisch
  • Patent number: 5948088
    Abstract: Each of a plurality of device or agents connected to a computer system bus is provided with a mechanism for unilaterally and dynamically limiting the depth of a pipeline of the bus. Each agent includes a state machine which indicates whether the bus is in a throttled state, a stalled state or a free state. When in a free state, an agent having control of the bus may transmit any number of bus transactions and the depth of the pipeline may therefore increase. In the throttled state, the agent may transmit only a single bus transaction from the throttled state, the state machine always transitions either to the stalled state or to the free state. In the stalled state, no agents may transmit transactions onto the bus and the depth of the pipeline therefore cannot increase and instead may decrease with time as previously issued transactions are drained from the bus.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: September 7, 1999
    Assignee: Intel Corporation
    Inventors: Nitin Sarangdhar, Michael Rhodehamel, Matthew Fisch
  • Patent number: 5909699
    Abstract: Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: June 1, 1999
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Michael W. Rhodehamel, Amit A. Merchant, Matthew A. Fisch, James M. Brayton
  • Patent number: 5901297
    Abstract: An initialization mechanism for symmetric arbitration agents ensures that multiple agents on a bus are each initialized with a different arbitration counter value. The arbitration counter of each bus agent is used to keep track of which agent was the last or current owner of the bus and which agent will be the next owner of the bus. All bus agents agree on which agent will be the priority agent at system reset and thus be allowed first ownership of the bus. Each agent's arbitration counter is initialized according to each agent's own agent identification. The arbitration pins of the bus agents are interconnected such that each agent determines for itself a unique agent identification based on which pin of its arbitration pins is active at system reset and the maximum number of bus agents allowed on the bus. After determining its agent identification, each bus agent initializes its arbitration counter such that every agent agrees which agent is the priority agent.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: May 4, 1999
    Assignee: Intel Corporation
    Inventors: Matthew A. Fisch, Michael W. Rhodehamel, Nitin Sarangdhar
  • Patent number: 5896513
    Abstract: A computer system providing a universal architecture includes a processor card connected to a system bus of a host computer system. The processor card is adapted for insertion into a slot of the computer system and houses a processor and a bus bridge conversion device. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: April 20, 1999
    Assignee: Intel Corporation
    Inventors: Matthew A. Fisch, James E. Jacobson, Jr., Michael W. Rhodehamel
  • Patent number: 5845107
    Abstract: A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on the pipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: December 1, 1998
    Assignee: Intel Corporation
    Inventors: Matthew A. Fisch, James E. Jacobson, Jr., Michael W. Rhodehamel
  • Patent number: 5834956
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: November 10, 1998
    Assignee: Intel Corporation
    Inventors: Chakrapani Pathikonda, Matthew A. Fisch, Javed S. Barkatullah
  • Patent number: 5826067
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: October 20, 1998
    Assignee: Intel Corporation
    Inventors: Matthew A. Fisch, Chakrapani Pathikonda