Patents by Inventor Matthew A. Thompson
Matthew A. Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230333982Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.Type: ApplicationFiled: June 20, 2023Publication date: October 19, 2023Inventors: Abhijeet Ashok CHACHAD, David Matthew THOMPSON, Naveen BHORIA
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Patent number: 11789868Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.Type: GrantFiled: October 12, 2021Date of Patent: October 17, 2023Assignee: Texas Instruments IncorporatedInventors: Abhijeet Ashok Chachad, David Matthew Thompson, Naveen Bhoria, Pete Michael Hippleheuser
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Publication number: 20230325314Abstract: In described examples, a coherent memory system includes a central processing unit (CPU), and first and second level caches, each with a cache controller. The CPU is arranged to execute program instructions to manipulate data in at least a first or second secure context. Each of the first and second caches stores a secure code for indicating the secure context by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing the secure codes of respective lines of cache and executing a cache coherency operation in response. A requestor coupled to the second level cache may send a coherence read transaction to the second level cache controller, which upon an affirmative security check, generates a snoop read transaction and sends the same to the first level cache.Type: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Naveen Bhoria
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Publication number: 20230324142Abstract: Disclosed is an extended range multi-caliber in-bore laser boresight system for sighting in a firearm. The device includes one or more hollow cartridge cases that resemble a standard firearm case lacking a bullet, a laser module, and an external electronic package. The laser module fits within the hollow cartridge case and is positioned within a firearm chamber. The laser exits the hollow cartridge through the firearm barrel to aid with zeroing a firearm sighting system. The laser diode is powerful enough to be visible at extended ranges in bright sunlight. The inventive boresight system can be used for zeroing any desired caliber, such as from 5.56 NATO to .50 BMG at extended range.Type: ApplicationFiled: April 5, 2023Publication date: October 12, 2023Applicant: The United States of America, as represented by the Secretary of the NavyInventors: Brandon W. Rudolph, Matthew A. Thompson, Daniel S. Spoor
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Patent number: 11772804Abstract: A rotor system for an aircraft is described and includes an open rotor assembly comprising a plurality of rotor blades connected to a rotor mast; and a drive system for providing rotational energy to the open rotor assembly via the rotor mast. The drive system includes at least one electric motor for providing rotational energy to a motor shaft; and a gearbox connected to the drive shaft for receiving rotational energy from the at least one electric motor via the motor shaft and providing rotational energy to the rotor mast via a rotor shaft.Type: GrantFiled: January 13, 2021Date of Patent: October 3, 2023Assignee: TEXTRON INNOVATIONS INC.Inventors: Jonathan Andrew Knoll, George Matthew Thompson, Charles Hubert Speller, Grant Michael Beall
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Patent number: 11771498Abstract: A method of calculating leg length discrepancy of a patient including: receiving patient bone data associated with a lower body of the patient; identifying anatomical landmarks in the patient bone data; orienting a first proximal landmark and a second proximal landmark relative to each other and an origin in a coordinate system; aligning a first axis associated with a first femur and a second axis associated with a second femur with a longitudinal axis extending in a distal-proximal direction, wherein the first and second distal landmarks are adjusted according to the alignment of the first and second axes; calculating a distance between the first and second distal landmarks in the distal-proximal direction along the longitudinal axis; and displaying at least one of the distance or a portion of the patient bone data on a display screen.Type: GrantFiled: December 7, 2020Date of Patent: October 3, 2023Assignee: MAKO SURGICAL CORP.Inventors: Daniel Odermatt, Matthew Thompson
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Patent number: 11768733Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.Type: GrantFiled: February 14, 2022Date of Patent: September 26, 2023Assignee: Texas Instruments IncorporatedInventors: Abhijeet Ashok Chachad, David Matthew Thompson, Son Hung Tran
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Publication number: 20230297469Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.Type: ApplicationFiled: May 30, 2023Publication date: September 21, 2023Inventors: David Matthew THOMPSON, Abhijeet Ashok CHACHAD
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Publication number: 20230297506Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.Type: ApplicationFiled: May 30, 2023Publication date: September 21, 2023Inventors: Abhijeet Ashok CHACHAD, David Matthew THOMPSON, Timothy David ANDERSON, Kai CHIRCA
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Publication number: 20230300286Abstract: Systems and methods are provided for presenting subtitles. The systems and methods include accessing, by a user device, a video discovery graphical user interface that includes a plurality of videos; receiving a user input that gradually reduces volume of the user device; determining that the volume of the user device has gradually been reduced by the user input until a mute state has been reached in which audio output of the user device is disabled; and in response to determining that the volume of the user device has gradually been reduced until the mute state has been reached, automatically causing subtitles of a first video of the plurality of videos to be displayed during playback of the first video.Type: ApplicationFiled: May 22, 2023Publication date: September 21, 2023Inventors: Nathan Kenneth Boyd, Andrew Grosvenor Cooper, David Michael Hornsby, Georgiy Kassabli, Matthew Thompson
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Publication number: 20230296119Abstract: According to the present disclosure there is provided a liquid flow influencing duct arrangement comprising: a first duct section arranged to receive a liquid flow therethrough, the first duct section defining a first direction through the first duct section from a liquid inlet end to a liquid outlet end; a second duct section defining a second direction through the second duct section from a liquid inlet end to a liquid outlet end, the second duct section comprising a vortex generator surface, wherein the vortex generator surface is arranged to induce vortices in the liquid flow through the first duct section, wherein the duct arrangement further comprises a rotor housed in one of the duct sections.Type: ApplicationFiled: July 19, 2021Publication date: September 21, 2023Applicant: BAE SYSTEMS plcInventors: Matthew Thompson, Mehmet Atlar, Callum Stark, Moritz Troll, Weichao Shi
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Patent number: 11762683Abstract: A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.Type: GrantFiled: December 6, 2021Date of Patent: September 19, 2023Assignee: Texas Instruments IncorporatedInventors: Abhijeet Ashok Chachad, David Matthew Thompson
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Publication number: 20230291697Abstract: Systems and methods are provided for performing operations including: retrieving, by one or more processors, a plurality of content items; identifying a list of friends of a user on a messaging application; obtaining reaction data for each friend in the list of friends, the reaction data identifying a set of content items to which respective ones of the friends in the list of friends reacted; selecting, based on the reaction data, a first content item in the plurality of content items that is included in the set of content items to which respective ones of the friends in the list of friends reacted; and presenting the first content item to the user in a presentation arrangement of a graphical user interface.Type: ApplicationFiled: May 19, 2023Publication date: September 14, 2023Inventors: Newar Husam Al Majid, Nathan Kenneth Boyd, Laurent Desserrey, Matthew Thompson, Jeremy Voss
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Publication number: 20230272810Abstract: According to the present disclosure there is provided an arrangement for influencing liquid flow, the arrangement comprising: a first section selectively configurable to provide a vortex generator surface to induce vortices in the liquid flow. The arrangement further comprises a second section, wherein the first section and second section are movable relative to one another to provide the vortex generator surface.Type: ApplicationFiled: July 19, 2021Publication date: August 31, 2023Applicant: BAE SYSTEMS plcInventors: Weichao Shi, Mehmet Atlar, Callum Stark, Matthew Thompson, Mortiz Troll, Leon Malcolm Sweet
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Patent number: 11740930Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions.Type: GrantFiled: April 5, 2022Date of Patent: August 29, 2023Assignee: Texas Instruments IncorporatedInventors: Abhijeet Ashok Chachad, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan
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Patent number: 11737894Abstract: A registration system including a bone pin guide and a bone pin clamp. The bone pin guide may include a guide body, a first guide including a first guide through-hole having a first longitudinal axis, and a second guide including a second guide through-hole having a second longitudinal axis. The bone pin guide may guide first and second bone pins into a bone via the first and second guides. The bone pin clamp may include a clamp body, first, second, and third clamp through-holes extending through the clamp body, a plurality of registration indents defined on the clamp body, and a clamping mechanism including at least one adjustable fastener. The bone pin clamp may receive the first and second bone pins in the first and third clamp through-holes and guide a third bone pin into the bone via the second clamp through-hole.Type: GrantFiled: March 2, 2021Date of Patent: August 29, 2023Assignee: MAKO SURGICAL CORP.Inventors: Zhu Wu, Sunil Gupta, Ta-Cheng Chang, Zenan Zhang, Kevin Bechtold, Matthew Thompson, Eric Branch, Varun Chandra, Ahmet Bagci
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Publication number: 20230264807Abstract: According to the present disclosure there is provided an arrangement for influencing fluid flow, the arrangement comprising: a first section selectively configurable to provide a vortex generator surface, the vortex generator surface comprising a series of laterally aligned projections, to induce vortices in the liquid flow.Type: ApplicationFiled: July 19, 2021Publication date: August 24, 2023Applicant: BAE SYSTEMS plcInventors: Weichao Shi, Mehmet Atlar, Callum Stark, Moritz Troll, Matthew Thompson, Leon Malcolm Sweet
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Publication number: 20230254907Abstract: Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI.Type: ApplicationFiled: March 21, 2023Publication date: August 10, 2023Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Daniel Brad Wu
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Publication number: 20230251975Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.Type: ApplicationFiled: April 3, 2023Publication date: August 10, 2023Inventors: Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Abhijeet Ashok Chachad, Hung Ong
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Patent number: 11722480Abstract: In certain embodiments, a distance threshold may be adjusted, and authentication may be performed based on the adjusted distance threshold. In some embodiments, an authentication request from a first user device associated with a user may be received. First location information of the first user device and second location information of a second user device may be obtained. A distance between the first and second user devices may be determined based on the first and second location information. A distance threshold may be adjusted based on whether such location information is obtained over the same wireless network, whether such information is obtained over a public wireless network, whether an IP address from which such location information is obtained matches a stored IP address, or other criteria. The user may be authenticated based on a comparison of the distance to the adjusted distance threshold.Type: GrantFiled: May 19, 2022Date of Patent: August 8, 2023Assignee: Capital One Services, LLCInventors: Paul Y. Moreton, Ryan Fox, Matthew Thompson