Patents by Inventor Matthew Colburn
Matthew Colburn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100173033Abstract: An imprint lithography template may be used to form an imprinted layer in a light curable liquid disposed on a substrate. During use, the template may be disposed within a template holder. The template holder may include a body with an opening configured to receive the template, a support plate, and an actuator system coupled to the body. The actuator system may be configured to alter a physical dimension of the template during use.Type: ApplicationFiled: March 2, 2010Publication date: July 8, 2010Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: Todd Bailey, Byung J. Choi, Matthew Colburn, S. V. Sreenivasan, C. Grant Willson, John Ekerdt
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Publication number: 20090239334Abstract: A method of manufacturing a memory device is provided that in one embodiment includes providing an interlevel dielectric layer including a first via containing a memory material; forming at least one insulating layer on an upper surface of the memory material and the interlevel dielectric layer; forming an cavity through a portion of a thickness of the at least one insulating layer; forming a copolymer mask in at least the cavity, the copolymer mask including at least one opening that provides an exposed surface of a remaining portion of the at least one insulating layer that overlies the memory material; etching the exposed surface of the remaining portion of the at least one insulating layer to provide a second via to the memory material; and forming a conductive material within the second via in electrical contact with the memory material.Type: ApplicationFiled: March 20, 2008Publication date: September 24, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew J. Breitwisch, Matthew Colburn, Eric Joseph, Chung Hon Lam, Deborah A. Neumayer, Alejandro G. Schrott
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Publication number: 20080199816Abstract: Disclosed herein is an automatic fluid dispensing method and system for dispensing fluid on the surface of a plate-like material, or substrate, including a semiconductor wafer for imprint lithography processes. The dispensing method uses fluid dispenser and a substrate stage that may generate relative lateral motions between a fluid dispenser tip a substrate. Also described herein are methods and devices for creating a planar surface on a substrate using a substantially unpatterned planar template.Type: ApplicationFiled: July 9, 2007Publication date: August 21, 2008Applicant: THE UNIVERSITY OF TEXAS BOARD OF REGENTSInventors: Byung J. Choi, S. V. Sreenivasan, C. Grant Willson, Matthew Colburn, Todd Bailey, John Ekerdt
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Publication number: 20080095878Abstract: The present invention includes a template comprising a plurality of protrusions and a plurality of recessions with a distance between a zenith of any of the plurality of protrusions and a nadir of any one of the plurality of recessions being less than 250 nm.Type: ApplicationFiled: June 11, 2007Publication date: April 24, 2008Applicant: BOARD OF REGENTS, UNIVERSITY OF TEXAS SYSTEMInventors: Todd Bailey, Byung Choi, Matthew Colburn, S.V. Sreenivasan, C. Willson, John Ekerdt
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Publication number: 20080038915Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.Type: ApplicationFiled: August 31, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel EDELSTEIN, Matthew COLBURN, Edward COONEY, Timothy DALTON, John FITZSIMMONS, Jeffrey GAMBINO, Elbert HUANG, Michael LANE, Vincent MCGAHAY, Lee NICHOLSON, Satyanarayana NITTA, Sampath PURUSHOTHAMAN, Sujatha SANKARAN, Thomas SHAW, Andrew SIMON, Anthony STAMPER
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Publication number: 20080038923Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: ApplicationFiled: September 6, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel EDELSTEIN, Matthew COLBURN, Edward COONEY, Timothy DALTON, John FITZSIMMONS, Jeffrey GAMBINO, Elbert HUANG, Michael LANE, Vincent MCGAHAY, Lee NICHOLSON, Satyanarayana NITTA, Sampath PURUSHOTHAMAN, Sujatha SANKARAN, Thomas SHAW, Andrew SIMON, Anthony STAMPER
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Publication number: 20080020546Abstract: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.Type: ApplicationFiled: September 27, 2007Publication date: January 24, 2008Applicant: International Business Machines CorporationInventors: Edward COONEY, Vincent McGahay, Thomas Shaw, Anthony Stamper, Matthew Colburn
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Publication number: 20070264588Abstract: The present invention includes an imprint lithography system for impinging a flux of light upon a liquid to polymerize the liquid, the system including, a source of light producing the flux of light; and a template having overlay marks being disposed between the liquid and the source of light and being opaque to the flux of light, with a pitch of the overlay marks establishing a polarization of the flux of light such that the flux of light impinges upon and polymerizes the liquid in superimposition with the overlay marks.Type: ApplicationFiled: June 9, 2004Publication date: November 15, 2007Applicant: Board of Regents, The University of Texas SystemInventors: Sidlgata Sreenivasan, Byung-Jin Choi, Matthew Colburn, Todd Bailey
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Publication number: 20070148598Abstract: A method for fabricating a dual damascene structure includes providing a multi-layer photoresist stack comprising a first photoresist layer and a second photoresist layer, wherein each photoresist layer has a distinct dose-to-clear value, exposing said photoresist stack to one or more predetermined patterns of light, and developing said photo-resist layers to form a multi-tiered structure in the photo-resist layers.Type: ApplicationFiled: December 24, 2005Publication date: June 28, 2007Inventors: Matthew Colburn, Dario Goldfarb
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Publication number: 20070138640Abstract: Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR?Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R? are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.Type: ApplicationFiled: February 19, 2007Publication date: June 21, 2007Inventors: Nirupama Chakrapani, Matthew Colburn, Christops Dimitrakopculos, Dirk Pfeiffer, Sampath Purushothaman, Satyanarayana Nitta
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Publication number: 20060267208Abstract: A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.Type: ApplicationFiled: April 17, 2006Publication date: November 30, 2006Inventors: Matthew Colburn, Timothy Dalton, Elbert Huang, Simon Karecki, Satya Nitta, Sampath Purushothaman, Katherine Saenger, Maheswaran Surendra
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Publication number: 20060264036Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: ApplicationFiled: July 24, 2006Publication date: November 23, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Tomothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu
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Publication number: 20060258147Abstract: A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.Type: ApplicationFiled: April 17, 2006Publication date: November 16, 2006Inventors: Matthew Colburn, Timothy Dalton, Elbert Huang, Simon Karecki, Anna Karecki, Satya Nitta, Sampath Purushothaman, Katherine Saenger, Maheswaran Surendra
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Publication number: 20060258159Abstract: A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.Type: ApplicationFiled: May 16, 2005Publication date: November 16, 2006Applicant: International Business Machines CorporationInventors: Matthew Colburn, Ricardo Donaton, Conal Murray, Satyanarayana Nitta, Sampath Purushothaman, Sujatha Sankaran, Theodorus Eduardus Fransiscus Standaert, Xiao Liu
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Publication number: 20060244146Abstract: Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.Type: ApplicationFiled: June 26, 2006Publication date: November 2, 2006Applicant: International Business Machines CorporationInventor: Matthew Colburn
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DEVELOPMENT OR REMOVAL OF BLOCK COPOLYMER OR PMMA-b-S-BASED RESIST USING POLAR SUPERCRITICAL SOLVENT
Publication number: 20060228653Abstract: Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier or chlorodiflouromethane itself in supercritical form. The invention also includes a method of forming a nano-structure including exposing a polymeric film to a polar supercritical solvent to develop at least a portion of the polymeric film. The invention also includes a method of removing a poly(methyl methacrylate-b-styrene) (PMMA-b-S) based resist using a polar supercritical solvent.Type: ApplicationFiled: April 12, 2005Publication date: October 12, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Colburn, Dmitriy Shneyder, Shahab Siddiqui -
Publication number: 20060157898Abstract: A method (and resultant structure) of forming a plurality of masks, includes creating a reference template, using imprint lithography to print at least one reference template alignment mark on all of a plurality of mask blanks for a given chip set, and printing sub-patterns on each of the plurality of mask blanks, and aligning the sub-patterns to the at least one reference template alignment mark.Type: ApplicationFiled: January 18, 2005Publication date: July 20, 2006Applicant: International Business Machines CorporationInventors: Matthew Colburn, Yves Martin, Charles Rettner, Theodore van Kessel, Hematha Wickramasinghe
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Publication number: 20060145400Abstract: An apparatus (and method) for referencing a surface of a workpiece during imprint lithography, includes an air bearing for mechanically referencing a surface of the workpiece, and a lithographic template coupled to the air bearing.Type: ApplicationFiled: January 4, 2005Publication date: July 6, 2006Applicant: International Business Machines CorporationInventors: Matthew Colburn, Yves Martin, Theodore van Kessel, Hematha Wickramasinghe
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Publication number: 20060147820Abstract: An apparatus (and method) for forming a pattern on a workpiece, includes an optical phase contrast image sensor, and an imprint lithography system coupled to the optical phase contrast image sensor for laterally aligning an imprint template feature relative to the workpiece.Type: ApplicationFiled: January 4, 2005Publication date: July 6, 2006Applicant: International Business Machines CorporationInventors: Matthew Colburn, Yves Martin, Theodore van Kessel, Hematha Wickramasinghe
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Patent number: 7060324Abstract: The present invention includes a method of moving a liquid between a substrate extending in a first plane and a template extending in a second plane. More specifically, the method may include forming an oblique angle between the first plane and the second plane, reducing a distance between the substrate and the template such that the template is in contact with a portion of the liquid at a desired location, and creating a dispersion of the liquid away from the desired location.Type: GrantFiled: January 13, 2004Date of Patent: June 13, 2006Assignee: Board of Regents, The University of Texas SystemInventors: Todd Bailey, Byung J. Choi, Matthew Colburn, Sidlgata V. Sreenivasan, C. Grant Willson, John Ekerdt