Abstract: A printhead assembly for a printing device is provided that includes a printhead comprising non-volatile memory elements. The memory elements include memristive elements. Each memristive element includes an active region disposed between two electrodes. The active region includes a switching layer formed of a switching material capable of carrying a species of dopants and a conductive layer in electrical contact with the switching layer, the conductive layer being formed of a dopant source material that includes the species of dopants that are capable of drifting into the switching layer under an applied potential.

Abstract: A metal-insulator transition (MIT) latch includes a first electrode spaced apart from a second electrode and an MIT material disposed between said first and second electrodes. The MIT material comprises a negative differential resistance (NDR) characteristic that exhibits a discontinuous resistance change at a threshold voltage or threshold current. Either the first or second electrode is electrically connected to an electrical bias source regulated to set a resistance phase of the MIT material.

Abstract: A memristor includes a first electrode having a triangular cross section, in which the first electrode has a tip and a base, a switching material positioned upon the first electrode, and a second electrode positioned upon the switching material. The tip of the first electrode faces the second electrode and an active region in the switching material is formed between the tip of the first electrode and the second electrode.

Abstract: A multilayer structure is disclosed that includes a conductive layer, a layer of a negative differential resistance (NDR) material disposed above the conductive layer, a layer M2 disposed above the NDR material, a second layer of NDR material disposed above layer M2, and a conductive layer disposed above the second NDR layer. Layer M2 can include a conductive material interspersed with regions of a dielectric material or a layer of the dielectric material and regions of the conductive material disposed above and below the dielectric material.

Abstract: Chaotic oscillator-based random number generation is described. In an example, a circuit includes a negative differential resistance (NDR) device to receive an alternating current (AC) bias. The circuit further includes a capacitance in parallel with the NDR device, the capacitance having a value such that, in response to a direct current (DC) bias applied to the NDR device and the capacitance, a voltage across the capacitance oscillates with a chaotic period. The circuit further includes a random number generator to generate random numbers using samples of the voltage across the capacitance.

Abstract: A memristor with a controlled electrode grain size includes an adhesion layer, a first electrode having a first surface contacting the adhesion layer and a second surface opposite the first surface, in which the first electrode is formed of an alloy of a base material and at least one second material, and in which the alloy has a relatively smaller grain size than a grain size of the base material. The memristor also includes a switching layer positioned adjacent to the second surface of the first electrode and a second electrode positioned adjacent to the switching layer.

Abstract: A device (10) may include a semiconductor layer section (25) and a memory layer section (45) disposed above the semiconductor layer section (25). The semiconductor layer section (25) may include a processor (12; 412) and input/output block (16; 416), and the memory layer section (45) may include memristive memory (14; 300). A method of forming such device (10), and an apparatus (600) including such device (10) are also disclosed. Other embodiments are described and claimed.

Abstract: A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.

Abstract: Circuitry is provided that closely emulates biological neural responses. Two astable multivibrator circuits (AMCs), each including a negative differential resistance device, are coupled in series-circuit relationship. Each AMC is characterized by a distinct voltage-dependant time constant. The circuitry exhibits oscillations in electrical current when subjected to a voltage equal to or greater than a threshold value. Various oscillating waveforms can be produced in accordance with voltages applied to the circuitry.

Abstract: A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element.

Abstract: Circuitry is provided that closely emulates biological neural responses. Two astable multivibrator circuits (AMCs), each including a negative differential resistance device, are coupled in series-circuit relationship. Each AMC is characterized by a distinct voltage-dependant time constant. The circuitry exhibits oscillations in electrical current when subjected to a voltage equal to or greater than a threshold value. Various oscillating waveforms can be produced in accordance with voltages applied to the circuitry.

Abstract: A memristive Negative Differential Resistance (NDR) device includes a first electrode adjacent to a memristive matrix, the memristive matrix including an intrinsic semiconducting region and a highly doped secondary region, a Metal-Insulator-Transition (MIT) material in series with the memristive matrix, and a second electrode adjacent to the MIT material.

Abstract: A memory array with Metal-Insulator Transition (MIT) switching devices includes a set of row lines intersecting a set of column lines and a memory element disposed at an intersection between one of the row lines and one of the column lines. The memory element includes a switching layer in series with an MIT material. A method of accessing a target memory element within a memory array includes applying half of an access voltage to a row line connected to the target memory element, the target memory element comprising a switching layer in series with an MIT material, and applying an inverted half of the access voltage to a column line connected to the target memory element.

Abstract: A frequency source and a method of frequency generation employ a memristive negative differential resistance (M-NDR) voltage controlled oscillator (VCO). The frequency source includes a first M-NDR VCO of a plurality of memristive VCOs to provide a first signal having a first signal frequency. The frequency source further includes a second M-NDR VCO of the plurality to provide a second signal having a second signal frequency. The first and second M-NDR VCOs are interconnected with the plurality of memristive VCOs. The first and second M-NDR VCOs have independent programmable states and are connected to a common output of the frequency source. The method includes providing an M-NDR VCOs, where each M-NDR VCO includes an M-NDR device connected in parallel with a capacitance, and applying a bias voltage to activate a selected M-NDR VCO of the plurality to produce a frequency output.

Abstract: An electrical circuit component includes a first electrode, a plurality of second electrodes and a negative differential resistance (NDR) material. The first electrode and the plurality of second electrodes are connected to the NDR material and the NDR material is to electrically connect the first electrode to one of the plurality of second electrodes when a sufficient voltage is applied between the first electrode and the one of the plurality of second electrodes through the NDR material.

Abstract: Apparatus and methods related to memory resistors are provided. A feedback controller applies adjustment signals to a memristor. A non-volatile electrical resistance of the memristor is sensed by the feedback controller during the adjustment. The memristor is adjusted to particular values lying between first and second limiting values with minimal overshoot. Increased memristor service life, faster operation, lower power consumption, and higher operational integrity are achieved by the present teachings.

Abstract: A frequency source and a method of frequency generation employ a memristive negative differential resistance (M-NDR) voltage controlled oscillator (VCO). The frequency source includes a first M-NDR VCO of a plurality of memristive VCOs to provide a first signal having a first signal frequency. The frequency source further includes a second M-NDR VCO of the plurality to provide a second signal having a second signal frequency. The first and second M-NDR VCOs are interconnected with the plurality of memristive VCOs. The first and second M-NDR VCOs have independent programmable states and are connected to a common output of the frequency source. The method includes providing an M-NDR VCOs, where each M-NDR VCO includes an M-NDR device connected in parallel with a capacitance, and applying a bias voltage to activate a selected M-NDR VCO of the plurality to produce a frequency output.

Abstract: A semiconductor device for providing heat management may include a first electrode with low metal thermal conductivity and a second electrode with low metal thermal conductivity. A metal oxide structure which includes a transition metal oxide (TMO) may be electrically coupled to the first electrode and second electrode and the metal oxide structure may be disposed between the first electrode and second electrode. An electrically insulating sheath with low thermal conductivity may surround the metal oxide structure.

Abstract: A memory array with Metal-Insulator Transition (MIT) switching devices includes a set of row lines intersecting a set of column lines and a memory element disposed at an intersection between one of the row lines and one of the column lines. The memory element includes a switching layer in series with an MIT material. A method of accessing a target memory element within a memory array includes applying half of an access voltage to a row line connected to the target memory element, the target memory element comprising a switching layer in series with an MIT material, and applying an inverted half of the access voltage to a column line connected to the target memory element.

Abstract: A switchable junction (600) having an intrinsic diode (634) formed with a voltage dependent resistor (640) is disclosed. The switchable junction comprises a first electrode (618), a second electrode (622), and a memristive matrix (620) configured to form an electrical interface (626) with the first electrode (618). The electrical interface has a programmable conductance. The voltage dependent resistor (640) is in electrical contact with the memristive matrix (620). The voltage dependent resistor is configured to form a rectifying diode interface (628) with the second electrode (622).