Patents by Inventor Matthew Dewey
Matthew Dewey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113161Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).Type: ApplicationFiled: December 14, 2023Publication date: April 4, 2024Inventors: Willy RACHMADY, Cheng-Ying HUANG, Matthew V. METZ, Nicholas G. MINUTILLO, Sean T. MA, Anand S. MURTHY, Jack T. KAVALIEROS, Tahir GHANI, Gilbert DEWEY
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Patent number: 11929435Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.Type: GrantFiled: August 30, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Harold Kennel, Tahir Ghani
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Patent number: 11923290Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.Type: GrantFiled: June 26, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Siddharth Chouksey, Gilbert Dewey, Nazila Haratipour, Mengcheng Lu, Jitendra Kumar Jha, Jack T. Kavalieros, Matthew V. Metz, Scott B Clendenning, Eric Charles Mattson
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Patent number: 11923410Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).Type: GrantFiled: October 4, 2021Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey
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Patent number: 11647835Abstract: A storage assembly includes top and bottom walls, a pair of end walls extending between the top and bottom walls and cooperating with the top and bottom walls to define an interior space, and at least one end surface configured to closely interfit with at least one end surface of an adjacent storage assembly that is substantially similar to the storage assembly at a predefined angular orientation such that a longitudinal axis of the storage assembly is angularly offset from a longitudinal axis of the adjacent storage assembly when the at least one end surface of the storage assembly is interfit with the at least one surface of the adjacent storage assembly The storage assembly may also include a pair of interior walls and a handle relief extending into the top wall and/or a frame assembly located between one of the end walls and one of the interior walls.Type: GrantFiled: March 30, 2020Date of Patent: May 16, 2023Assignee: Smith System Manufacturing CompanyInventors: David Williams, Roger John Carr, Michael Risdall, Robert Scharfenkamp, Jack Wayne Johnson, Matthew Dewey
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Patent number: 11172757Abstract: A leg assembly for a table includes a support that is configured to couple to a table worksurface. A leg member engages the support and is movable with respect to the support such that the leg assembly is configured to support the table worksurface above a floor surface. A first friction reduction member is attached to a first end of the leg member. A second friction reduction member is configured to attach to a second end of the leg member. The first and second ends are configured to alternately engage the support from one another such that the leg member is reversibly received by the support and such that the first friction reduction member abuts the floor surface when the second end of the leg member engages the support, and the second friction reduction member abuts the floor surface when the first end of the leg member engages the support.Type: GrantFiled: March 23, 2020Date of Patent: November 16, 2021Assignee: Smith System Manufacturing Company, Inc.Inventors: Robert Scharfenkamp, Michael Risdall, Jack Wayne Johnson, Matthew Dewey
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Publication number: 20210298471Abstract: A storage assembly includes top and bottom walls, a pair of end walls extending between the top and bottom walls and cooperating with the top and bottom walls to define an interior space, and at least one end surface configured to closely interfit with at least one end surface of an adjacent storage assembly that is substantially similar to the storage assembly at a predefined angular orientation such that a longitudinal axis of the storage assembly is angularly offset from a longitudinal axis of the adjacent storage assembly when the at least one end surface of the storage assembly is interfit with the at least one surface of the adjacent storage assembly The storage assembly may also include a pair of interior walls and a handle relief extending into the top wall and/or a frame assembly located between one of the end walls and one of the interior walls.Type: ApplicationFiled: March 30, 2020Publication date: September 30, 2021Inventors: David Williams, Roger John Carr, Michael Risdall, Robert Scharfenkamp, Jack Wayne Johnson, Matthew Dewey
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Publication number: 20210289937Abstract: A leg assembly for a table includes a support that is configured to couple to a table worksurface. A leg member engages the support and is movable with respect to the support such that the leg assembly is configured to support the table worksurface above a floor surface. A first friction reduction member is attached to a first end of the leg member. A second friction reduction member is configured to attach to a second end of the leg member. The first and second ends are configured to alternately engage the support from one another such that the leg member is reversibly received by the support and such that the first friction reduction member abuts the floor surface when the second end of the leg member engages the support, and the second friction reduction member abuts the floor surface when the first end of the leg member engages the support.Type: ApplicationFiled: March 23, 2020Publication date: September 23, 2021Applicant: SMITH SYSTEM MANUFACTURING COMPANY INC.Inventors: Robert Scharfenkamp, Michael Risdall, Jack Wayne Johnson, Matthew Dewey
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Patent number: 9069702Abstract: Apparatus, methods, and other embodiments associated with reducing read starvation that is supported by a multi-purpose buffer managed by a least recently used (LRU) data structure are described. One example method includes changing how certain retired pages are added back into the LRU. The dual-purpose buffer may be used in data de-duplication to support satisfying ingest requests and to support satisfying read requests. The method may also include controlling the LRU to allocate active ingest pages and active read pages from the head of the LRU. The method may also include controlling the LRU to cause the active ingest page and the active read page to re-enter the LRU at the tail of the LRU. Unlike conventional approaches, the method may also include controlling the LRU to cause a retired ingest page to re-enter the LRU at a location other than the tail (e.g., head) of the LRU.Type: GrantFiled: May 3, 2012Date of Patent: June 30, 2015Inventors: Todd Pisek, Matthew Dewey
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Patent number: 8702202Abstract: An apparatus and method for liquid-phase dispensing of layers onto a substrate of an electronic device. An absorbent material reduces or eliminates splatter of printing material on the substrate during continuous printing operations. The absorbent material can be regenerated by exposure of new surface area or vacuum drawing of printing material through the absorbent material.Type: GrantFiled: December 28, 2009Date of Patent: April 22, 2014Assignee: E. I. du Pont de Nemours and CompanyInventors: James Daniel Tremel, Matthew Stainer, Matthew Dewey Hubert
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Publication number: 20130297898Abstract: Apparatus, methods, and other embodiments associated with reducing read starvation that is supported by a multi-purpose buffer managed by a least recently used (LRU) data structure are described. One example method includes changing how certain retired pages are added back into the LRU. The dual-purpose buffer may be used in data de-duplication to support satisfying ingest requests and to support satisfying read requests. The method may also include controlling the LRU to allocate active ingest pages and active read pages from the head of the LRU. The method may also include controlling the LRU to cause the active ingest page and the active read page to re-enter the LRU at the tail of the LRU. Unlike conventional approaches, the method may also include controlling the LRU to cause a retired ingest page to re-enter the LRU at a location other than the tail (e.g., head) of the LRU.Type: ApplicationFiled: May 3, 2012Publication date: November 7, 2013Applicant: Quantum CorporationInventors: Todd Pisek, Matthew Dewey
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Patent number: 8504533Abstract: Example apparatus and methods concern de-duplication reference tag reconciliation associated with garbage collection and/or reference health checking. One example method may include accessing data associated with members of a set of references to blocks of data stored by a data de-duplication system. The method may process the first data to manipulate a Bloom filter into a state from which membership in the set of references can be assessed. The method may also include accessing a block identifier identified with a member of the set of blocks of data stored by the data de-duplication system and assessing membership in the set of references for the block identifier by querying the Bloom filter with the block identifier. If the block is not referenced, as determined by querying the Bloom filter, then the method may include performing a block reclamation action on the unreferenced block.Type: GrantFiled: December 20, 2011Date of Patent: August 6, 2013Inventors: Matthew Dewey, Roderick B. Wideman
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Publication number: 20130159261Abstract: Example apparatus and methods concern de-duplication reference tag reconciliation associated with garbage collection and/or reference health checking. One example method may include accessing data associated with members of a set of references to blocks of data stored by a data de-duplication system. The method may process the first data to manipulate a Bloom filter into a state from which membership in the set of references can be assessed. The method may also include accessing a block identifier identified with a member of the set of blocks of data stored by the data de-duplication system and assessing membership in the set of references for the block identifier by querying the Bloom filter with the block identifier. If the block is not referenced, as determined by querying the Bloom filter, then the method may include performing a block reclamation action on the unreferenced block.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Applicant: QUANTUM CORPORATIONInventors: Matthew Dewey, Roderick B. Wideman
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Publication number: 20110223340Abstract: An apparatus and method for liquid-phase coating of layers onto a substrate of an electronic device. Electo-form nozzles containing a body and disc are arranged in an array to perform multiple depositions on the substrate. A low solids mixture produces a very thin dried film of electronic materials.Type: ApplicationFiled: November 18, 2009Publication date: September 15, 2011Applicant: E. I. DU PONT DE NEMOURS AND COMPANYInventors: James Daniel Tremel, Mtthew Stainer, Matthew Dewey Hubert
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Patent number: 8002939Abstract: Methods and devices are provided for improving the encapsulation processes for an organic electronic device.Type: GrantFiled: December 29, 2005Date of Patent: August 23, 2011Assignee: E. I. du Pont de Nemours and CompanyInventors: James Daniel Tremel, Matthew Dewey Hubert
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Publication number: 20100270919Abstract: Described are encapsulation assemblies useful for electronic devices having a substrate and an active area, the encapsulation assembly comprising a barrier sheet and a barrier structure that contains an adhesive and a discreet material, wherein the barrier structure is configured so as to substantially hermetically seal an electronic device when in use thereon. The barrier structure bonds the encapsulation assembly to the electronic device and contains a getter material to protect against environmental degradation.Type: ApplicationFiled: December 20, 2008Publication date: October 28, 2010Inventors: Matthew Dewey Hubert, James Daniel Tremel, Kyle D. Frischknecht, Nugent Truong
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Publication number: 20100188459Abstract: An apparatus and method for liquid-phase dispensing of layers onto a substrate of an electronic device. An absorbent material reduces or eliminates splatter of printing material on the substrate during continuous printing operations. The absorbent material can be regenerated by exposure of new surface area or vacuum drawing of printing material through the absorbent material.Type: ApplicationFiled: December 28, 2009Publication date: July 29, 2010Applicant: E. I. DU PONT DE NEMOURS AND COMPANY.Inventors: James Daniel Tremel, Matthew Stainer, Matthew Dewey Hubert
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Patent number: D1003641Type: GrantFiled: October 29, 2021Date of Patent: November 7, 2023Assignee: SMITH SYSTEM MANUFACTURING COMPANYInventors: Jack Wayne Johnson, Randall Joseph Kastalanych, John R. Kutzke, Robert Scharfenkamp, Matthew Dewey
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Patent number: D1008711Type: GrantFiled: October 29, 2021Date of Patent: December 26, 2023Assignee: SMITH SYSTEM MANUFACTURING COMPANYInventors: Jack Wayne Johnson, Randall Joseph Kastalanych, John R. Kutzke, Robert Scharfenkamp, Matthew Dewey
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Patent number: D1011096Type: GrantFiled: October 29, 2021Date of Patent: January 16, 2024Assignee: SMITH SYSTEM MANUFACTURING COMPANYInventors: Jack Wayne Johnson, Randall Joseph Kastalanych, John R. Kutzke, Robert Scharfenkamp, Matthew Dewey